Public Version
SDRAM Controller (SDRC) Subsystem
www.ti.com
Table 10-113. SMS_REVISION
Address Offset
0x0000 0000
Physical Address
0x6C00 0000
Instance
SMS
Description
This register contains the IP revision code. IP revision code is defined at design time
Type
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
REV
Bits
Field Name
Description
Type
Reset
31:8
RESERVED
Read returns 0.
R
0x000000
7:0
REV
IP revision code
R
See
(1)
[7:4] Major revision
[3:0] Minor revision
Examples: 0x10 for 1.0, 0x21 for 2.1
(1)
TI internal data
Table 10-114. Register Call Summary for Register SMS_REVISION
SDRAM Controller (SDRC) Subsystem
•
Table 10-115. SMS_SYSCONFIG
Address Offset
0x0000 0010
Physical Address
0x6C00 0010
Instance
SMS
Description
This register controls the various parameters of the Interconnect.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
AUTOIDLE
RESERVED
RESERVED
RESERVED
SIDLEMODE
SOFTRESET
Bits
Field Name
Description
Type
Reset
31:9
RESERVED
Write 0s for future compatibility. Read returns 0s.
RW
0x000000
8
RESERVED
Write 0s for future compatibility. Read returns 0s.
RW
0x0
7:5
RESERVED
Write 0s for future compatibility. Read returns 0s.
RW
0x0
4:3
SIDLEMODE
Power management Req/Ack Control
RW
0x0
0x0: Force Idle - An idle request is acknowledged unconditionally
0x1: No Idle - An idle request is never acknowledged.
0x2: Smart Idle - Acknowledgment to an idle request is based on the
internal activity of the module
0x3: Reserved - Do not use.
2
RESERVED
Write 0s for future compatibility. Read returns 0.
RW
0x0
1
SOFTRESET
Software reset
RW
0x0
0x0: Normal mode (no reset applied)
0x1: Software reset is activated
0
AUTOIDLE
Internal interface clock gating strategy
RW
0x1
0x0: Interface clock is free-running
0x1: Automatic interface clock gating strategy is applied, based on the
interconnect activity
2302
Memory Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
Содержание OMAP36 Series
Страница 174: ...174 List of Tables SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 692: ...692 MPU Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1084: ...1084 IVA2 2 Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1990: ...1990 2D 3D Graphics Accelerator SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2334: ...2334 Memory Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2700: ...2700 Memory Management Units SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2868: ...2868 HDQ 1 Wire SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2974: ...2974 UART IrDA CIR SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3054: ...3054 Multichannel SPI SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3462: ...3462 MMC SD SDIO Card Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3508: ...3508 General Purpose Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3584: ...3584 Initialization SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3648: ...3648 Debug and Emulation SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...