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MMC/SD/SDIO Register Manual
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Bits Field Name Description Type Reset
3 Reserved Reserved bit field. Do not write any value R 0
2 BGE Block gap event. RW 0
When a stop at block gap is requested (MMCi. MMCHS_HCTL [16] SBGR
bit), this bit is automatically set when transaction is stopped at the block gap
during a read or write operation.
This event does not occur when the stop at block gap is requested on the
last block.
In read mode, a 1-to-0 transition of the mmci_dat line active status
(MMCi.
MMCHS_PSTATE [2] DLA bit) between data blocks generates a
Block gap event interrupt.
Read 0x0: No block gap event
Write 0x0: Status bit unchanged
Read 0x1: Transaction stopped at block gap
Write 0x1: Status is cleared
1 TC Transfer completed. RW 0
This bit is always set when a read/write transfer is completed or between two
blocks when the transfer is stopped due to a stop at block gap request
(MMCi.
MMCHS_HCTL [16] SBGR bit).
This bit is also set when exiting a command in a busy state (if the command
has a busy notification capability).
In Read mode: This bit is automatically set on completion of a read transfer
(MMCi.
MMCHS_PSTATE [9] RTA bit).
In write mode: This bit is set automatically on completion of the mmci_dat
line use (MMCi.
MMCHS_PSTATE [2] DLA bit).
Read 0x0: No transfer complete
Write 0x0: Status bit unchanged
Read 0x1: Data transfer complete
Write 0x1: Status is cleared
0 CC Command complete. RW 0
This bit is set when a 1-to-0 transition occurs in the register command inhibit
(MMCi.
MMCHS_PSTATE [0] CMDI bit)
If the command is a type for which no response is expected, then the
command complete interrupt is generated at the end of the command. A
command timeout error (MMCi.
MMCHS_STAT [16] CTO bit) has higher
priority than command complete (MMCi. MMCHS_STAT [0] CC bit).
If a response is expected but none is received, then a command timeout
error is detected and signaled instead of the command complete interrupt.
Read 0x0: No Command complete
Write 0x0: Status bit unchanged
Read 0x1: Command complete
Write 0x1: Status is cleared
Table 24-70. Register Call Summary for Register MMCHS_STAT
MMC/SD/SDIO Integration
• Clocks : [0] [1] [2] [3]
• Interrupt Requests : [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18]
MMC/SD/SDIO Functional Description
• Data Buffer : [19] [20] [21] [22] [23] [24]
• Transfer or Command Status and Error Reporting : [25] [26]
• Busy Timeout For R1b, R5b Response Type : [27]
• Busy Timeout After Write CRC Status : [28]
• Write CRC Status Timeout : [29]
• Read Data Timeout : [30] [31]
• Boot Acknowledge Timeout : [32] [33] [34] [35] [36] [37]
• MMC CE-ATA Command Completion Disable Management : [38]
MMC/SD/SDIO Use Cases and Tips
• Programming Flow : [39]
3452MMC/SD/SDIO Card Interface SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated