Texas Instruments OMAP36 Series, Техническое справочное руководство

Страница: 1183 / 3738

camisp-249
Virtual channel 0
Virtual channel 1
Virtual channel 2
Virtual channel 3
Data ID (format)
Context 0
Context 1
Context 2
Context 3
Context 4
Context 5
Context 6
Context 7
Public Version
www.ti.com
Camera ISP Functional Description
Figure 6-70. Camera ISP CSI2 Virtual Channel to Context
Each context consists of eight registers: six registers to control the corresponding context and two to log
and enable events from the context. All registers in a context can be modified at any time; however,
modifications apply only from the start of the following frame.
A context can be enabled independently by writing 1 in the CSI2_CTx_CTRL1 [0] CTX_EN bit field; writing
0 disables the corresponding context.
When acquiring frames on a context, users can write the number of frames to capture in the
CSI2_CTx_CTRL1 [15:8] COUNT bit field. Acceptable values are 0:255; 0 stands for infinite capture (no
count). After each frame acquired, the count value is decremented by 1. When the count value reaches 0,
the
CSI2_CTx_IRQSTATUS [6] FRAME_NUMBER_IRQ event is set and the CTX_EN bit is set to 0. To
write a value in the COUNT bit field, the CSI2_CTx_CTRL1 [4] COUNT_UNLOCK bit must be set to 1. If
the COUNT_UNLOCK value is 0, a write in the COUNT bit field has no effect.
The CSI2_CTx_CTRL3 [15:0] LINE_NUMBER bit field configures the generation of the
CSI2_CTx_IRQSTATUS [7] LINE_NUMBER_IRQ event. The CSI2_CTx_CTRL1 [1] LINE_MODULO bit
configures how the LINE_NUMBER event is generated:
• 0: The event is generated one time by frame.
• 1: The event is generated modulo LINE_NUMBER (the event can be generated more than once in a
frame).
During a frame capture, the CSI2_CTx_CTRL2 [31:16] FRAME_NUMBER bit field shows the number that
identifies the frame received.
6.4.3.8 Camera ISP CSI2 DMA Engine
The CSI2 receiver integrates its own DMA engine with dedicated FIFO.
Global DMA configuration (single access, non-streaming and posted writes) is common to the eight
channels and is defined in the
CSI2_CTRL register. Configuration of the ping-pong address and the offset
between lines is specific for a given context; therefore, each context has its own DMA configuration
registers.
The DMA engine supports the following requests:
•
Single write
When an element (the size depends on the data type) is present in the FIFO, the DMA engine initiates a
single write.
All single requests sent to the interconnect are back-to-back requests with no idle, if the FIFO has enough
data to supply the DMA.
The DMA starts to write in memory using the CSI2_CTx_DAT_PING_ADDR [31:5] ADDR bit field for the
first frame to be transferred and then uses the CSI2_CTx_DAT_PONG_ADDR [31:5] ADDR bit field and
the ping address alternately. So, the first frame uses the ping address, the second frame uses the pong
address, the third frame uses the ping address, and so on.
1183 SWPU177N – December 2009 – Revised November 2010 Camera Image Signal Processor
Copyright © 2009–2010, Texas Instruments Incorporated