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IVA2.2 Subsystem Basic Programming Model
NOTE: The CCERRINT event follows the same conventions as other TPCC interrupt outputs. When
the error interrupt condition transitions from a no-errors-are-set state to at least one error set,
the error output (CCERRINT) pulses high for one TPCC clock cycle. If additional errors are
latched before the original error is cleared by the user, the TPCC does not generate
additional interrupt pulses. The software must poll all bits during execution of the ISR, and
clear all error conditions, so that subsequent error pulses can be generated by the TPCC
block.
Error interrupts can be set and/or reevaluated by writes to the TPCC_EEVAL register.
TPTC Block
The TPTC can also detect several error conditions:
• Read status or write status errors in the TPTCj_ERRSTAT [0] BUSERR status bit
• TR error in the TPTCj_ERRSTAT [2] TRERR status bit
• MMR address error in the TPTCj_ERRSTAT [3] MMRAERR status bit
Errors are recorded in the TPTCj_ERRSTAT register, regardless of whether they are enabled. They can
be cleared from the TPTCj_ERRSTAT register only by writing 1 to the corresponding bit of the
IVA_TPTCj_ERRCLR register.
The error details register (IVA_ TPTCj_ERRDET ) contains additional information about the first read status
error or write status error detected. Future errors are bit-recorded until the TPTCj_ERRDET register is
cleared.
If read status and write status are returned to the TPTC in the same cycle, the read or write status value
that has an error (nonzero) is latched in the
TPTCj_ERRDET register and the TPTCj_ERRSTAT [0]
BUSERR bit is set. If both read and write status are nonzero, the write status is given priority for setting
the
TPTCj_ERRDET register. The TPTCj_ERRDET register is cleared by writing 1 to the
TPTCj_ERRCLR [0] BUSERR bit.
If an error is enabled (by the TPTCj_ERREN register bits), the first occurrence of an enabled error
generates a pulsed interrupt to the CPU by the TCERRINT event output (TCERRINT0 with EVT39 for
TPTG0 and TCERRINT1 with EVT40 for TPTG1, respectively; see
Table 5-3 ). Subsequent errors do not
generate a new pulse until all accumulated errors are cleared by the CPU. The CPU clears bits in the
TPTCj_INTSTAT register by writing 1 to the corresponding bit(s) of the TPTCj_NTCLR register.
5.4.11.3 Error Reporting for the L3 Interconnect
L3 interconnect out-of-band errors are also reported by the external L3 interrupt signal
(l3_ia_iva2_initSError_o). This signal corresponds to the EVT84 event and is directly connected to the
IVA2.2_nIRQ[39] DSP CPU interrupt line. For more information about L3 interconnect error reporting, see
Chapter 9 , Interconnect.
5.4.12 Recommendations for Static Settings
The following static settings are recommended:
• SYSC. SYSC_LICFG0 .DMATRUECOMPEN = 1; // DMA last write is nonposted.
• SYSC. SYSC_LICFG0 .GEMTRUECOMPEN = 1; // DSP last write is nonposted.
• SYSC. SYSC_LICFG0 .GEMBURSTOPTEN = 1; // DSP burst optimization
Ensure that the following setting is carefully set:
• All 2D DMA transfers source and/or destination are to a VRFB view (tiling structure):
– // DMA 2D burst optimization
– SYSC. SYSC_LICFG0 .DMA2DOPTEN = 1
NOTE: If the preceding condition is not set accurately, setting the DMA2DOPTEN optimization can
degrade performance.
803 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated