Texas Instruments OMAP36 Series, Техническое справочное руководство

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SDRAM Controller (SDRC) Subsystem
Table 10-105. Programmable AC Parameters (continued)
SDRC Description Range
AC Parameter (Clock Ticks)
tRP PRECHARGE command period (Row Precharge time) 0 - 7
tRCD ACTIVE to READ or WRITE delay (Row-to-Column Delay time) 0 - 7
tRRD ACTIVE bank A to ACTIVE bank B delay 0 - 7
tWR WRITE Recovery time (also known as tDPL) 0 - 7
tDAL Auto precharge write re precharge time 0 - 31
tWTR Internal Write to Read command delay (also known as tCDLR) 1 - 3
tCKE CKE min pulse width (high and low pulse width) 1 - 7
tXP Exit Power-Down to next valid command delay 1 - 7
tXSR Self-Refresh exit to next valid command delay 0 - 255
Example of configuration:
If there is a minimum tRC requirement of 88 ns at 100 MHz, 88/10 = 9 (8.8 is rounded up).
Therefore, nine clock cycles must be set.
The SDRC AC parameters described in Table 10-106 are hard-coded.
Table 10-106. Nonprogrammable AC Parameters
SDRC Description Range Comment
AC Parameter (Clock Ticks)
tMRD MODE REGISTER SET command period 3
tDQSS Write command to first DQS latching 1 (0.75 - 1.25 CK)
transition
tRPRE Read preamble 1 (0.9 - 1.1 CK) DQS is held low for read when driving on
the same cycle as the read command is
stopped.
NOTE: The SDRC uses tXSR only when exiting self-refresh mode, regardless of the first command
issued. The SDRC systematically inserts an autorefresh command before it serves the first
request.
10.2.5.3.4 DLL/CDL Configuration
The DLL unit is configured by writing to the SDRC. SDRC_DLLA_CTRL register. This register contains the
following fields:
• FIXEDDELAY
• MODEFIXEDDELAYINITLAT
• DLLMODEONIDLEREQ
• DLLIDLE
• ENADLL
• LOCKDLL
To support low-frequency DDR access, set the DLL in fixed delay mode by setting the
SDRC_DLLA_CTRL [2] LOCKDLL bit to 0x1. In this mode, the SDRC_DLLA_CTRL [31:24] FIXEDELAY
field allows the programming of the CDL delay. This provides the correct fixed DCB code based on the
input frequency. Only the voltage precharge part of the DLL is still used to control the CDL instances in
this mode, but the control loop is broken and the voltage control is inactive.
2269 SWPU177N – December 2009 – Revised November 2010 Memory Subsystem
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