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IVA2.2 Subsystem Basic Programming Model
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• IVA. CAVLC_STRMWDU : This register resets the first call of the CAVLC function. This includes the
upper half of the 32-bit stream word register. The value is less than 32 bits and specifies how many
remaining bits are not written in the bitstream after iVLCD completion.
• IVA. CAVLC_STRMWDL : This register resets the first call of the CAVLC function. This includes the
lower half of the 32-bit stream word register. The value is less than 32 bits and specifies how many
remaining bits are not written in the bitstream after iVLCD completion.
Because the encoded bitstream does not always finish as a complete 32-bit word at the end of 1-MB
encoding,
IVA. CAVLC_STRMWDU contains the upper short of the 32-bit word,
IVA. CAVLC_STRMWDL contains the lower short, and CAVLC_BITPTR indicates how many bits are
valid, starting from the MSB of IVA. CAVLC_STRMWDU .
• IVA. CAVLC_IBUFSEL : This register specifies input port, output port, and swapping configuration. If the
CAVLC-generated bitstream is b0, b1... b15, b16... b31 ... (b0 is the first bit of the bitstream), and if the
stream byte swap bit in IBUF_SEL is 0, the first 32 bits of the bitstream are stored in a 32-bit memory
word as:
mem[31:24] mem[23:16] mem[15:8] mem[7:0]
|b16b23 |b24,..,b31 |b0,,b7 |b8,..,b15|
If the stream byte swap bit is 1,
mem[31:24] mem[23:16] mem[15:8] mem[7:0]
|b24...b31 |b16,..,b23 |b8, ..,b15 |b0,...,b7|
Initialize these registers each time the CALVC function is run:
•
IVA. CAVLC_GO_REG : Setting this bit starts the CAVLC module. It is the same as a Start_sequence.
• IVA. CAVLC_MBTYPE : This register contains the MB type and the coded block pattern. The codec
block pattern field has 6 bits. The cbp configuration is the same as that of the H.264 standard.
• IVA. CAVLC_HDPTR : Set a pointer on Hmem memory to read the MB header symbol and its length.
• IVA. CAVLC_HDCOUNT : This register contains the number of MB header pairs. The range of this
value is 0 to 1023.
• IVA. CAVLC_NAPTR : Set a pointer on Hmem memory from which nA parameters are stored.
• IVA. CAVLC_NBPTR : Set a pointer on Hmem memory from which nB parameters are stored.
• IVA. CAVLC_COEFFPTR : Set a pointer on Ibuf0 memory to read residual data.
The following registers do not need to be initialized; they contain only information about the encoded
bitstream:
•
IVA. CAVLC_NUMTTL : This register specifies the total number of bits generated. This value considers
remaining bits not yet written in the bitstream.
• IVA. CAVLC_NUMHD : This register specifies how many bits are generated from the MB header.
• IVA. CAVLC_NUMRESI : This register specifies how many bits are generated from residual data.
5.4.8 Interrupt Management
5.4.8.1 Interrupt Flow in IVA2.2 Subsystem
The DSP megamodule interrupt controller (IC) detects, combines, and routes up to 128 system events
(internal and external) to the 12 DSP CPU interrupt lines. For more information about interrupt mapping of
the IVA2.2 subsystem (internal and external interrupts), see
Table 5-3 .
In addition to performing handshaking for chip-level wake-up sequencing for waking from static
power-down, the DSP megamodule WUGEN module internally routes the interrupt request to the IC
module. This occurs because the WUGEN module is the only DSP megamodule module in the CORE
power domain to enable the powered-off DSP subsystem to be awakened after the DSP receives an
interrupt from any device peripherals.
Figure 5-29 shows the IVA2.2 subsystem interrupt flow with the main WUGEN and IC registers used for
event generation.
780 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010
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