Texas Instruments OMAP36 Series, Техническое справочное руководство

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PRCM Register Manual
Table 3-274. CM_POLCTRL
Address Offset 0x0000 009C
Physical Address 0x4800 529C Instance Global_Reg_CM
Description This register allows setting the polarity of device outputs control signals.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
CLKOUT2_POL
Bits Field Name Description Type Reset
31:1 RESERVED Write 0s for future compatibility. Read returns 0. R 0x00000000
0 CLKOUT2_POL Controls the external output clock 2 polarity when RW 0x0
disabled
0x0: sys_clkout2 is gated low when inactive
0x1: sys_clkout2 is gated high when inactive
Table 3-275. Register Call Summary for Register CM_POLCTRL
PRCM Functional Description
• External Output Clock2 (sys_clkout2) Control : [0]
PRCM Basic Programming Model
• CM_POLCTRL (CM Polarity Control Register) : [1]
PRCM Register Manual
• Global_Reg_CM Register Summary : [2]
3.8.1.14 NEON_CM Registers
3.8.1.14.1 NEON_CM Register Summary
Table 3-276. NEON_CM Register Summary
Register Name Type Register Width Address Offset Physical Address Reset Type
(Bits)
CM_IDLEST_NEON R 32 0x0000 0020 0x4800 5320 C
CM_CLKSTCTRL_NEON RW 32 0x0000 0048 0x4800 5348 W
3.8.1.14.2 NEON_CM Registers
541 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
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