Public Version
Display Subsystem Register Manual
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Bits
Field Name
Description
Type
Reset
0x0:
Digital output disabled (at the end of the current field if
interlace output when the bit is reset)
0x1:
Digital output enabled
0
LCDENABLE
LCD enable
RW
0
0x0:
LCD output disabled (at the end of the frame when the
bit is reset)
0x1:
LCD output enabled
Table 7-149. Register Call Summary for Register DISPC_CONTROL
Display Subsystem Environment
•
•
•
Video Port Used on Command Mode
Display Subsystem Integration
•
•
Display Subsystem Functional Description
•
:
•
•
:
Display Subsystem Basic Programming Model
•
•
Display Controller Basic Programming Model
:
[12] [13] [14] [15] [16] [17] [18]
•
•
Graphics Layer Configuration Registers
:
•
:
•
•
:
•
Video Up-/Down-Sampling Configuration
:
•
:
•
LCD-Specific Control Registers
•
•
:
•
:
•
:
[41] [42] [43] [44] [45] [46] [47]
•
LCD Spatial/Temporal Dithering
:
•
•
TV Set-Specific Control Registers
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:
•
•
:
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Command Mode Transfer Example 1
:
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Command Mode Transfer Example 2
:
•
•
•
Video Encoder Programming Sequence
Display Subsystem Use Cases and Tips
•
Configure DISPC Timing, Window, and Color
:
[76] [77] [78] [79] [80] [81] [82] [83] [84]
•
Enable Video Mode Using the DISPC Video Port
:
•
Configure DISPC Timing, Window, and Color
:
[88] [89] [90] [91] [92] [93] [94] [95] [96]
•
Send Frame Data to LCD Panel Using Automatic TE
:
Display Subsystem Register Manual
•
Display Controller Register Mapping Summary
:
•
1832Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated