Public Version
Camera ISP Basic Programming Model
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6.5.3.2
Camera ISP CSI1/CCP2B Event and Status Checking
When an event occurs, the corresponding bit in the
(or
) register is set. Each event can be individually masked using the
register (
). Masked events are not transmitted to the
interrupt lane, but the
register (or
) is updated.
Events transmitted to the interrupt lane can be mapped to the ARM or DSP by unmasking the ISP_CSIB
bit in the ISP_IRQxENABLE (x = 0, 1). Depending on whether the event is mapped to the ARM or DSP
register, to clear an event, the following actions are required:
•
Clear the event at the CSI1/CCP2B receiver level by writing 1 to the corresponding bit in the
register (or
•
Clear the event at ISP level by writing 1 to the corresponding bit ISP_CSI1 in the ISP_IRQxENABLE (x
= 0, 1) register.
6.5.3.3
Camera ISP CSI1/CCP2B Register Accessibility During Frame Processing
There are two types of register accesses in the CSI1/CCP2B receiver:
•
Shadowed registers:
–
These registers/fields can be read and written (if the field is writable) at any time. However, written
values take effect only at the start of a frame. Reads return the most recent write, even though the
settings are not used until the next start of frame.
–
The shadowed registers are:
•
•
•
•
•
•
•
•
•
•
•
Busy-locked registers:
–
These registers/fields must not be written if the module is busy.
–
All register fields not listed as shadowed are busy-writable registers.
6.5.3.4
Camera ISP CSI1/CCP2B Enable/Disable the Hardware
The CSI1/CCP2B receiver is globally controlled by the
register. The bit fields in this register
must not be modified when the CSI1/CCP2B interface is active (except
[0] IF_EN):
•
To activate the CSI1/CCP2B interface:
–
[0] IF_EN = 0x1
–
Data acquisition starts on the following FSC synchronization code. Writing
[0] IF_EN
= 0x1 resets the output FIFO of the module; the reset is caused by the 0-to-1 edge transition.
•
To disable the CSI1/CCP2B interface:
–
[0] IF_EN = 0x0
–
The interface is disabled immediately if
[3] FRAME = 0x0.
–
If
[3] FRAME = 0x1 and
[19] CRC_EN = 0x0, the interface is
disabled after the FEC synchronization code is received.
–
If
[3] FRAME = 0x1 and
[19] CRC_EN = 0x1, the interface is
disabled only after the 16-bit CRC checksum and 16-bit pad data is received.
–
Before disabling the interface (IF_EN=0) it is advised to disable all active channels by writing
[0] CHAN_EN = 0x0. Otherwise, if IF_EN = 0 is set during a vertical blanking
period, the reception continues until the FEC synchronization code is received for all active
1248
Camera Image Signal Processor
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated