MMU-008
MMU-009
Public Version
MMU Functional Description
www.ti.com
•
A pointer to a second-level translation table that specifies individual translation properties based on
smaller pages within the 1MB page of memory. These pages can be either 64KB (large page) or 4KB
(small page). In this case, the actual translation parameters are specified in the second-level
translation table entry. The first-level translation table entry specifies only the base address of the
second-level translation table.
This hierarchical approach means that additional translation information for smaller pages must be
provided only when the pages are actually used.
shows this hierarchy.
Figure 15-8. Translation Hierarchy
The structure of the first and second-level translation tables and their entries are described in more detail
in
, First-Level Translation Table, and
, Two-Level Translation.
15.3.3.2 First-Level Translation Table
The first-level translation table describes the translation properties for 1MB sections. To describe a 4GB
address range requires 4096 32-bit entries (so-called first-level descriptors).
The first-level translation table start address must be aligned on a multiple of the table size with a
128-byte minimum. Consequently, an alignment of at least 16K bytes is required for a complete
4096-entry table; that is, at least the last fourteen address bits must be zero.
The start address of the first-level translation table is specified by the so-called translation table base. The
table is indexed by the upper 12-bits of the virtual address. This mechanism is shown in
Figure 15-9. First-Level Descriptor Address Calculation
To summarize, the translation table base and the translation table index together define the first-level
descriptor address.
outlines the precise mechanism used to calculate this address.
2672
Memory Management Units
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
