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SDMA Functional Description
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For a read/write port size of 64 bits, the source or destination can be configured as packed for transfer
ESs of 8 bits (eight elements per access), 16 bits (four elements per access), and 32 bits (two
elements per access).
Depending on the start address and transfer length, the first or last packed access might be only partially
filled. This is indicated to the source or destination using the byte-enable signals.
11.4.5 Burst Transactions
Transfer performance can be improved, where the source or destination and addressing profile supports it,
by configuring the logical channel to perform burst transactions consisting of multiple instead of single
accesses. The channel can be programmed to use burst sizes equivalent to 16, 32, or 64 bytes through
the
register, with the read burst size being programmable independently of the write burst
size. Typically, the optimal burst size is 64 bytes (16 accesses for a 32-bit read/write port size or 8
accesses for a 64-bit read/write port size).
To obtain the maximum benefit from burst transactions, the source and destination start addresses should
be aligned with the burst size. If this is not the case, the start of the transfer can consist of a number of
smaller (single or burst) transactions until the first burst size boundary is reached.
Similarly, if the end of the transfer is not aligned on a burst size boundary, the final part of the transfer can
consist of a number of smaller transactions.
NOTE:
Except in the constant addressing mode, the source or destination must be specified as
packed for burst transactions to occur.
11.4.6 Endianism Conversion
The source and destination are each specified as little-endian or big-endian through the
register for the particular logical channel. If the endianism of the source and destination differ, and the
logical channel ES is less than the SDMA module read/write port size, an endianism conversion is applied
to the data before it is written to the destination.
When transferring data between a source and a destination with different endianism, it is important to
specify an ES that is equal to the type of data being transferred to preserve the correct data image at the
destination.
In the system, endianism conversion can be performed in more than one place. It is possible to inform the
source and/or destination to lock the endianism (that is, to not perform a conversion) through the logical
DMA channel
register.
11.4.7 Transfer Synchronization
A logical channel can be programmed for either software-triggered or hardware synchronized transfers.
11.4.7.1 Software Synchronization
A transfer is software-triggered when the logical channel is set up and started by software. To specify a
software-triggered transfer, set the channel DMA register bits
[4:0] and
[20:19] to
0. The transfer starts as soon as the DMA register bit
[7] is set (that is, enters the scheduling
process).
11.4.7.2 Hardware Synchronization
A transfer is hardware-synchronized if the logical channel activation is driven by hardware requests from
either the source or destination target. A hardware synchronized transfer is specified by configuring the
DMA request line number in the channel
register to a value that corresponds to the DMA
request line from the source or destination that generates the DMA requests. The DMA request numbers
to be configured are specified in the DMA request mapping (see
).
2353
SWPU177N – December 2009 – Revised November 2010
SDMA
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