Public Version
Display Subsystem Register Manual
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Bits
Field Name
Description
Type
Reset
18
SYNC_LOST_IRQ
Synchronization with Video port is lost (Video mode only)
RW
0x0
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
17
ACK_TRIGGER_IRQ
Acknowledge Trigger
RW
0x0
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
16
TE_TRIGGER_IRQ
Tearing Effect Trigger
RW
0x0
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
15
LP_RX_TO_IRQ
Interrupt for Low Power Rx Time out
RW
0x0
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
14
HS_TX_TO_IRQ
Interrupt for high-speed Tx Time out.
RW
0x0
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
13
RESERVED
Write 0s for future compatibility.
RW
0x0
Reads returns 0.
12:11
RESERVED
Write 0s for future compatibility.
RW
0x0
Reads returns 0.
10
COMPLEXIO_
Error signaling from complex I/O: status of the complex I/O
R
0x0
ERR_IRQ
errors received from the complex I/O(events are defined in
).
0x0: READS: Event is false.
0x1: READS: Event is true (pending).
9
PLL_RECAL_IRQ
PLL recalibration event (assertion of recalibration signal from the
RW
0x0
DSI PLL Control module)
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
8
PLL_UNLOCK_IRQ
PLL un-lock event (de-assertion of lock signal from the DSI PLL
RW
0x0
Control module)
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
7
PLL_LOCK_IRQ
PLL lock event (assertion of lock signal from the DSI PLL
RW
0x0
Control module)
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
6
RESERVED
Write 0s for future compatibility.
RW
0x0
Reads returns 0.
5
RESYNCHRONIZATION_
Video mode resynchronization
RW
0x0
IRQ
1912
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated