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Display Subsystem Basic Programming Model
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value at reset time is 0x0. The horizontal resolution is one pixel because the base address is aligned
on pixel size boundary. In case of YCbCr 4:2:2 formats, the resolution is 2 pixels. In case of RGB24
packed format, the resolution is 4 pixels. The vertical resolution is one line. The register
DSS.DISPC_VIDn_BA0 defines the base address of the even field, and DSS.DISPC_VIDn_BA1
defines the base of the odd field in the case of an external synchronization and based on the value of
the input signal DISPC_FID and the polarity. To improve system throughput, the base address should
be aligned on the burst size boundary.
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Video FIFO threshold (DSS.
register): The low threshold
(DSS.
[11:0] VIDFIFOLOWTHRESHOLD) and the high threshold
(DSS.
[27:16] VIDFIFOHIGHTHRESHOLD) values define the FIFO
DMA behavior. When the low level is reached, one or more requests are issued to the L3-based
interconnect to fill up the FIFO to reach the high threshold. A request is issued as long as the FIFO
has enough space available to accept a burst. The DMA engine then waits until the low level is
reached to restart the requests. By setting the DSS.
[14] FIFOMERGE bit to 1, users
merge the three FIFOs (GFX, VID1, and VID2). In this case, the low threshold (the
DSS.
[11:0] VIDFIFOLOWTHRESHOLD bit field with n
corresponding to the active video channel 1 or 2) and the high threshold
(DSS.
[27:16] VIDFIFOHIGHTHRESHOLD bit field with n
corresponding to the active video channel 1 or 2) values must be programmed with a multiplier factor
of three (3 x value). By default, the FIFOs are not merged (the DSS.
[14] FIFOMERGE
bit reset value is 0).
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Video buffer width (DSS.
[10:0] VIDORGSIZEX): The default value at
reset time is 0x0 (1 pixel). The buffer width in system memory is from 1 up to 2048 pixels. All the
integer values in the range [1:2048] are allowed. Software users must program this bit field to the value
minus 1.
•
Video buffer height (DSS.
[26:16] VIDORGSIZEY): The default value at
reset time is 0x0 (1 pixel). The buffer height in system memory is from 1 up to 2048 pixels. All the
integer values in the range [1:2048] are allowed. Software users must program this field to the value
minus 1.
•
Video data endianness (DSS.
[17] VIDENDIANNESS bit, with n=1 or 2):
This bit indicates the endianness (little or big) of the video pixels. The default value at reset time is 0x0
(little endian).
7.5.3.3.2 Video Configuration Register
The following shadow registers define video layer n (with n = 1 or 2) configuration:
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DSS.
•
DSS.
•
DSS.
•
DSS.
•
DSS.
•
DSS.
•
DSS.
(with i = 0 to 7)
•
DSS.
(with i = 0 to 7)
•
DSS.DISPC_VIDn_CONV_COEFi (with i = 0 to 4)
•
The video layer n (with n = 1 or 2) is enabled/disabled by setting/resetting the
DSS.
[0] VIDENABLE field. If the video layer is disabled, the video window
does not exist on the screen and the whole video pipeline and DMA are inactive. Before enabling the
video layer, a valid configuration must be set. After a register change, either the
DSS.
[5] GOLCD bit must be set. The
software must wait for the hardware to reset the bit before setting this bit. The software reset is not
recommended because the application cannot ensure that the bit is reset before the hardware reset.
7.5.3.3.3 Video Window Attributes
The following fields define the attributes of video window n:
1714
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
