Texas Instruments OMAP36 Series, Technical Reference Manual

Page: 3194 / 3738

Public Version
McBSP Register Manual
www.ti.com
Bits Field Name Description Type Reset
5 ROVFLSTAT Receive Buffer Overflow (ROVFLSTAT bit is set to one RW 0x0
when receive buffer overflow; the data which is written
while overflow condition is discarded).
Writing 1 to this bit clears the bit.
0x0: receive buffer NOT overflow
0x1: receive buffer overflow; Writing 1 to this bit clears
the bit.
4 RUNDFLSTAT Receive Buffer Underflow (RUNDFLSTAT bit is set to RW 0x0
one when read operation is performed to the receive data
register while receive buffer is empty; data read while
underflow condition is undefined).
Writing 1 to this bit clears the bit.
0x0: read operation is performed to the receive data
register while receive buffer is NOT empty
0x1: read operation is performed to the receive data
register while receive buffer is empty; Writing 1 to this bit
clears the bit.
3 RRDY Receive Buffer Threshold Reached (RRDY bit is set to RW 0x0
one when the receive buffer occupied locations are equal
or above the THRSH1_REG value).
Writing 1 to this bit clears the bit.
0x0: receive buffer occupied locations are below the
THRSH1_REG value).
0x1: receive buffer occupied locations are equal or above
the THRSH1_REG value). Writing 1 to this bit clears the
bit.
2 REOF Receive End Of Frame (REOF is set to one when a RW 0x0
complete frame was received).
Writing 1 to this bit clears the bit.
0x0: complete frame was NOT received
0x1: complete frame was received; Writing 1 to this bit
clears the bit.
1 RFSR Receive Frame Synchronization (RFSR bit is set to one RW 0x0
when a new receive frame synchronization is asserted).
Writing 1 to this bit clears the bit.
0x0: new receive frame synchronization is NOT asserted
0x1: new receive frame synchronization is asserted;
Writing 1 to this bit clears the bit.
0 RSYNCERR Receive Frame Synchronization Error (RSYNCERR is set RW 0x0
to one when a receive frame synchronization error is
detected).
Writing 1 to this bit clears the bit.
0x0: receive frame synchronization error is NOT detected
0x1: receive frame synchronization error is detected.
Writing 1 to this bit clears the bit.
Table 21-117. Register Call Summary for Register MCBSPLP_IRQSTATUS_REG
McBSP Integration
• Power Management : [0] [1] [2] [3]
• Interrupt Requests : [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17]
McBSP Functional Description
• Enable/Disable the Transmit and Receive Processes : [18] [19] [20] [21]
• Introduction : [22] [23] [24] [25] [26] [27] [28]
• Overrun in the Receiver : [29] [30] [31]
• Unexpected Receive Frame-sync Pulse : [32] [33]
• Underflow in the Receiver : [34] [35]
• Underflow in the Transmitter : [36] [37] [38]
• Unexpected Transmit Frame-sync Pulse : [39]
• Overflow in the Transmitter : [40]
3194Multi-Channel Buffered Serial Port SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated