Public Version
Camera ISP Register Manual
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Bits
Field Name
Description
Type
Reset
31
FLUSH
CCDC memory flush
RW
0
Writing '1' in this bit flushes the CCDC memories in the
central resource SBL. The SBL memories are always
flushed by the end of frame. However, there are cases
where the end of frame cannot be detected.
30
JPEG_FLUSH
JPEG flush
RW
0
When a camera module outputs a JPEG bit stream, this
bit needs to be set because the bitstream length may not
be a multiple of 32 bits. Enabling this bit ensures that no
data stay in the design internal FIFOS.
29
CCDC_WEN_POL
Sets the polarity of the CCDC WEN bit.
RW
0
0x0: Active low
0x1: Active high
28
SBL_SHARED_RPORTB
Controls SBL shared read port B access
RW
0
0x0: Read port used by preview module dark frame read
0x1: Read port used by CCDC module lens shading
compensation data read
27
SBL_SHARED_RPORTA
Controls SBL shared read port A access
RW
0
0x0: Read port used by preview module data read
0x1: Read port used by CSI1 module data read
26
SBL_SHARED_WPORTC
Controls SBL shared write port C access
RW
0
0x0: CSI1/CCP2B : CCP2 protocol engine
0x1: CSI2C : CSI2C protocol engine
25:24
CBUFF1_BCF_CTRL
Bandwidth control feedback loop configuration register
RW
0x0
0x0: Disabled.
0x1: The BCF signal of CBUFF1 stalls the response
phase of the CSI1/CCP2B Interconnect read master port.
0x2: The BCF signal of CBUFF1 stalls the request phase
of the CSI1/CCP2B Interconnect read master port.
0x3: The BCF signal of CBUFF1 stalls the request and
response phase of the CSI1/CCP2B Interconnect read
master port.
23:22
CBUFF0_BCF_CTRL
Bandwidth control feedback loop configuration register
RW
0x0
0x0: Disabled.
0x1: The BCF signal of CBUFF0 stalls the response
phase of the CSI1/CCP2B Interconnect read master port.
0x2: The BCF signal of CBUFF0 stalls the request phase
of the CSI1/CCP2B Interconnect read master port.
0x3: The BCF signal of CBUFF0 stalls the request and
response phase of the CSI1/CCP2B Interconnect read
master port.
21
SBL_AUTOIDLE
Sets the SBL autoidle mode
RW
1
0x0: Disabled
0x1: Enabled
20
SBL_WR0_RAM_EN
This bit controls the SBL module WRITE0 RAM used by
RW
0
the RESIZER module. If the RESIZER module is
disabled, this bit shall be set to '0' to save power.
0x0: RAM is disabled
0x1: RAM is enabled
19
SBL_WR1_RAM_EN
This bit controls the SBL module WRITE1 RAM. If the
RW
0
RESIZER module is the only module enabled to perform
memory to memory resize operations, this bit shall be set
to '0' to save power.
0x0: RAM is disabled
0x1: RAM is enabled
1320
Camera Image Signal Processor
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated