Texas Instruments OMAP36 Series, Technical Reference Manual

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Camera ISP Register Manual
Bits Field Name Description Type Reset
31 HS_VS_IRQ HS or VS synchro event
(1)
R/W/1to 0
READS: Clr
0: event is false
1: event is true
WRITES
0: status bit unchanged
1: status bit reset
30 RESERVED Write 0s for future compatibility. Read returns 0. RW 0
29 OCP_ERR_IRQ ISP interconnect error. R/W/1to 0
READS: Clr
0: event is false
1: event is true
WRITES
0: status bit unchanged
1: status bit reset
28 MMU_ERR_IRQ MMU error. R/W/1to 0
If event is true, one needs to read the MMU_IRQSTATUS Clr
register to know the event source.
READS:
0: event is false
1: event is true
WRITES
0: status bit unchanged
1: status bit reset
27:26 RESERVED Write 0s for future compatibility. Read returns 0. R/W/1to 0
Clr
25 OVF_IRQ Central Resource SBL overflow R/W/1to 0
If event is true, one needs to check the SBL_PCR Clr
register to know the source. One needs to clear the
SBL_PCR register first before clearing this bit.
READS:
0: event is false
1: event is true
WRITES
0: status bit unchanged
1: status bit reset
24 RSZ_DONE_IRQ RESIZER module - resizer processing done event. R/W/1to 0
READS: Clr
0: event is false
1: event is true
WRITES
0: status bit unchanged
1: status bit reset
23:22 RESERVED Write 0s for future compatibility. Read returns 0. R/W/1to 0
Clr
21 CBUFF_IRQ A circular buffer event is pending. Check submodule's RW 0
interrupt status register. W1toClr
READS:
0: event is false
1: event is true
WRITES
0: status bit unchanged
1: status bit reset
20 PRV_DONE_IRQ PREVIEW module - processing done event. R/W/1to 0
READS: Clr
0: event is false
1: event is true
WRITES
0: status bit unchanged
1: status bit reset
(1)
This event is detected on the incoming HS/VS signals before the CCDC. Therefore, it cannot be used in BT656 mode.
1315 SWPU177N – December 2009 – Revised November 2010 Camera Image Signal Processor
Copyright © 2009–2010, Texas Instruments Incorporated