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SDRAM Controller (SDRC) Subsystem
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Table 10-178. Register Call Summary for Register SDRC_EMR2_p
SDRAM Controller (SDRC) Subsystem
•
:
•
Extended Mode Register 2 (EMR2)
:
•
Mode Register Programming and Modes of Operation
•
•
•
:
Table 10-179. SDRC_ACTIM_CTRLA_p
Address Offset
0x0000 009C + (0x0000 0028 * p)
Index
p = 0 to 1
Physical Address
0x6D00 009C + (0x0000 0028 * p)
Instance
SDRC
Description
The ac timing control register A sets the ac parameter values in clock cycle units to best match the memory
characteristics.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
TRFC
TRC
TRAS
TRP
TRCD
TRRD
TDPL
TDAL
RESERVED
Bits
Field Name
Description
Type
Reset
31:27
TRFC
Autorefresh to active
RW
0x00
26:22
TRC
Row cycle time
RW
0x00
21:18
TRAS
Row active time
RW
0x0
17:15
TRP
Row precharge time
RW
0x0
14:12
TRCD
Row to column delay time
RW
0x0
11:9
TRRD
Active to active command period
RW
0x0
8:6
TDPL
Data-in to precharge command (write recovery time tWR)
RW
0x0
5
RESERVED
Write 0s for future compatibility. Read returns 0.
RW
0x0
4:0
TDAL
Data-in to active command
RW
0x00
Table 10-180. Register Call Summary for Register SDRC_ACTIM_CTRLA_p
SDRAM Controller (SDRC) Subsystem
•
:
•
Low-Power SDR/Mobile DDR Initialization Sequence
•
Table 10-181. SDRC_ACTIM_CTRLB_p
Address Offset
0x0000 00A0 + (0x0000 0028 * p)
Index
p = 0 to 1
Physical Address
0x6D00 00A0 + (0x0000 0028 * p)
Instance
SDRC
Description
The ac timing control register B sets the ac parameter values in clock cycle unit, to best match the memory
characteristics
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
TWTR
TCKE
TXP
TXSR
RESERVED
RESERVED
2328
Memory Subsystem
SWPU177N – December 2009 – Revised November 2010
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