Texas Instruments OMAP36 Series, Technical Reference Manual

Page: 470 / 3738

Public Version
PRCM Register Manual
www.ti.com
Table 3-127. CM_AUTOIDLE_PLL_MPU
Address Offset 0x0000 0034
Physical Address 0x4800 4934 Instance MPU_CM
Description This register provides automatic control over the DPLL1 activity.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
AUTO_MPU_DPLL
Bits Field Name Description Type Reset
31:3 RESERVED Write 0s for future compatibility. Read returns 0. R 0x00000000
2:0 AUTO_MPU_DPLL DPLL1 automatic control; Other enums: Reserved RW 0x0
0x0: Auto control disabled
0x1: DPLL1 is automatically put in low power stop mode
when the MPU clock is not required anymore. It is also
restarted automatically.
Table 3-128. Register Call Summary for Register CM_AUTOIDLE_PLL_MPU
PRCM Functional Description
• DPLL Modes : [0]
• DPLL Source-Clock Controls : [1]
PRCM Basic Programming Model
• CM_AUTOIDLE_PLL_ <processor_name> (Processor DPLL Autoidle Register) : [2]
PRCM Register Manual
• MPU_CM Register Summary : [3]
Table 3-129. CM_CLKSEL1_PLL_MPU
Address Offset 0x0000 0040
Physical Address 0x4800 4940 Instance MPU_CM
Description This register provides controls over the MPU DPLL.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED MPU_DPLL_MULT MPU_DPLL_DIV
RESERVED
MPU_CLK_SRC
Bits Field Name Description Type Reset
31:22 RESERVED Write 0s for future compatibility. Read returns 0. R 0x000
21:19 MPU_CLK_SRC Selects the DPLL1 bypass source clock; Other enums: RW 0x1
Reserved
0x1: DPLL1_FCLK is CORE_CLK divided by 1
0x2: DPLL1_FCLK is CORE_CLK divided by 2
0x4: DPLL1_FCLK is CORE_CLK divided by 4
470 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated