Texas Instruments OMAP36 Series, Technical Reference Manual

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Source selection/division Hardware control Software control
DPLL1_ALWON_FCLK
DPLL2_ALWON_FCLK
DPLL3_ALWON_FCLK
DPLL5_ALWON_FCLK
HC
HC
HC
HC GS
SYS_CLK
CORE_CLK
DPLL1_FCLK
DPLL2_FCLK
HC
HC
PRCM.CM_CLKSEL1_PLL_MPU[21:19]
MPU_CLK_SRC
Ratios: 1/2/4
PRCM.CM_CLKSEL1_PLL_IVA2[21:19]
IVA2_CLK_SRC
Ratios: 1/2/4
prcm-059
DPLL4_ALWON_FCLK
HC GS
PRCM.PRM_CLKSRC_CTRL[8]
DPLL4_CLKINP_DIV
Ratios: 1/6.5
Public Version
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PRCM Functional Description
3.5.3.7.4 DPLL Source-Clock Controls
Figure 3-63 shows the clock controls for the DPLL power domain.
Figure 3-63. DPLL Power Domain Clock Controls
Table 3-48 shows the clock-gating controls for the DPLL power domain.
Table 3-48. DPLL Power Domain Clock-Gating Controls
Clock Name Reset Clock-Gating Control Gating Description
DPLL1_ALWON_FCLK Running PRCM. CM_AUTOIDLE_PLL_MPU [2:0] Gated if the DPLL is set to automatic active
AUTO_MPU_DPLL, control and enabled in lock mode while the
PRCM. CM_CLKEN_PLL_MPU [2:0] MPU power domain goes into retention or
EN_MPU_DPLL, and MPU domain off mode. Also gated if DPLL is set to
power state low-power bypass mode.
DPLL1_FCLK Stopped
DPLL2_ALWON_FCLK Stopped PRCM. CM_AUTOIDLE_PLL_IVA2 [2:0] Gated if the DPLL is set to automatic active
AUTO_IVA2_DPLL, control and enabled in lock mode while the
PRCM. CM_CLKEN_PLL_IVA2 [2 :0] IVA2 power domain goes into retention or
EN_IVA2_DPLL, and IVA2 power off mode. Also gated if DPLL is set to
domain power state low-power stop or bypass mode.
DPLL2_FCLK Stopped
DPLL3_ALWON_FCLK Running PRCM. CM_AUTOIDLE_PLL [2:0] Gated if the DPLL is set to automatic active
AUTO_CORE_DPLL, control and enabled in lock mode while the
PRCM. CM_CLKEN_PLL [2:0] CORE power domain is idle. Also gated if
EN_CORE_DPLL, and CORE domain DPLL is set to low-power or fast-relock
power clocks state bypass mode.
DPLL4_ALWON_FCLK Stopped PRCM. CM_AUTOIDLE_PLL [5:3] Gated if the DPLL is set to automatic active
AUTO_PERIPH_DPLL, control and enabled in lock mode while its
PRCM. CM_CLKEN_PLL [18:16] dependent clock is inactive. Also gated if
EN_PERIPH_DPLL, and depends on DPLL is set to low-power stop mode.
the clock-gating conditions of
DPLL4_M2_CLK
DPLL5_ALWON_FCLK Stopped PRCM. CM_AUTOIDLE2_PLL [2:0] Gated if the DPLL is set to automatic active
AUTO_PERIPH2_DPLL, control and enabled in lock mode while its
PRCM. CM_CLKEN2_PLL [2:0] dependent clock is inactive. Also gated if
EN_PERIPH2_DPLL, and depends on DPLL is set to low-power stop mode.
the clock-gating conditions of
DPLL5_M2_CLK
339 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
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