Texas Instruments OMAP36 Series, Technical Reference Manual

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PRCM Register Manual
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Table 3-121. CM_CLKEN_PLL_MPU
Address Offset 0x0000 0004
Physical Address 0x4800 4904 Instance MPU_CM
Description This register controls the DPLL1 modes.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED
RESERVED
EN_MPU_DPLL
EN_MPU_DPLL_LPMODE
EN_MPU_DPLL_DRIFTGUARD
Bits Field Name Description Type Reset
31:11 RESERVED Write 0s for future compatibility. Read returns 0. R 0x000000
10 EN_MPU_DPLL_LPMODE This bit allows to enable or disable the LP mode of the RW 0x0
MPU DPLL. Writting this bit to switch the mode between
LP or normal mode will take effect only when the DPLL
will have transition into the bypass or stop state, followed
by a lock or re-lock of the DPLL.
0x0: Disables the DPLL LP mode to re-enter the normal
mode at the following lock or re-lock sequence.
0x1: Enables the DPLL LP mode to enter the LP mode at
the following lock or re-lock sequence.
9:8 RESERVED RW 0x0
7:4 RESERVED Reserved RW 0x1
3 EN_MPU_DPLL_DRIFTGUARD This bit allows to enable or disable the automatic RW 0x0
recalibration feature of the MPU DPLL. The DPLL1 will
automatically start a recalibration process upon assertion
of the recal flag if this bit is set.
0x0: Disables the DPLL1 automatic recalibration mode
0x1: Enables the DPLL1 automatic recalibration mode
2:0 EN_MPU_DPLL DPLL1 control; Other enums: Reserved RW 0x5
0x5: Put the DPLL1 in low power bypass mode
0x7: Enables the DPLL1 in lock mode
Table 3-122. Register Call Summary for Register CM_CLKEN_PLL_MPU
PRCM Functional Description
• DPLL Modes : [0]
• DPLL Low-Power Mode : [1]
• Recalibration : [2]
• DPLL Source-Clock Controls : [3]
PRCM Basic Programming Model
• CM_CLKEN_PLL_<processor_name> (Processor DPLL Clock Enable Register) : [4] [5]
PRCM Register Manual
• MPU_CM Register Summary : [6]
468 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
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