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PRCM Basic Programming Model
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: Divider configuration for 120-MHz clock (120M_FCLK)
3.6.2.3.3 CM_CLKEN_PLL_<processor_name> (Processor DPLL Clock Enable Register)
The processor DPLL clock enable register allows the enabling or disabling of DPLL1 and DPLL2. It allows
an immediate setting of the DPLL.
The device has two DPLL clock enable registers, one for DPLL1 and one for DPLL2:
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: DPLL1 (MPU)
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: DPLL2 (IVA2)
The CM_CLKEN_PLL_<processor_name> register allows programmable control of the following DPLL
features:
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Low-power stop mode (only for DPLL2)/low-power bypass mode/lock mode selection
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Automatic recalibration enable/disable
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Programmable internal frequency range of the DPLL
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The DPLL LP mode can be enabled or disabled. However, switching between LP and normal mode is
effective only when the DPLL has performed a recalibration; therefore, the DPLL must lock or relock.
Also, the LP mode control is considered only during the following transitions:
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From bypass to lock
–
From stop mode to lock
–
From lock to relock
NOTE:
DPLL1 enters its internal power state (MNBYPASS) after being released from reset or when
a multiplier value of 0 or 1 is loaded into the DPLL. Therefore, even if the
[2:0] EN_MPU_DPLL bit field is reset to the low-power bypass mode,
DPLL1 automatically transitions to MNBYPASS mode, because the multiplier value (the
[18:8] MPU_DPLL_MULT bit field) resets to 0.
3.6.2.3.4 CM_CLKEN_PLL (DPLL Enable Register)
The DPLL enable register allows control of DPLL3, DPLL4, and DPLL5. It allows an immediate setting of
the DPLLs. This register controls the following features of the two DPLLs:
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DPLL operation mode:
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Low-power bypass, fast-relock bypass, and lock modes for DPLL3
–
Low-power bypass and lock modes for DPLL4
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Programmable automatic recalibration
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Programmable internal frequency range for the DPLL
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The DPLL3 output M3X2 and the DPLL4 outputs M2, M3, M4, M5, and M6 clock paths can be
powered down. However, the setting takes effect only when the output clock is gated. It is also
powered down whenever the DPLL is in stop mode, regardless of the software settings.
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The DPLL LP mode can be enabled or disabled. However, switching between LP and normal mode is
effective only when the DPLL has performed a recalibration; therefore, the DPLL must lock or relock.
Also, the LP mode control is considered only during the following transition:
–
From bypass to lock
–
From stop mode to lock
–
From lock to relock
3.6.2.3.5 CM_AUTOIDLE_PLL_ <processor_name> (Processor DPLL Autoidle Register)
The processor DPLL autoidle register allows the enabling/disabling of the automatic processor DPLL
activity control. In automatic mode, the DPLL automatically enters low-power stop mode when the DPLL
clock is not required. It is also restarted automatically.
The following are the device DPLL autocontrol registers:
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: DPLL1 autoidle mode control
404
Power, Reset, and Clock Management
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
