Texas Instruments OMAP36 Series, Technical Reference Manual

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PRCM Register Manual
Table 3-194. Register Call Summary for Register CM_IDLEST2_CKGEN
PRCM Basic Programming Model
• DPLL Clock Control Registers : [0]
PRCM Register Manual
• Clock_Control_Reg_CM Register Summary : [1]
Table 3-195. CM_AUTOIDLE_PLL
Address Offset 0x0000 0030
Physical Address 0x4800 4D30 Instance Clock_Control_Reg_CM
Description This register provides automatic control over the DPLL3 and DPLL4 activity.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
AUTO_CORE_DPLL
AUTO_PERIPH_DPLL
Bits Field Name Description Type Reset
31:6 RESERVED Write 0s for future compatibility. Read returns 0. R 0x0000000
5:3 AUTO_PERIPH_DPLL DPLL4 automatic control; Other enums: Reserved RW 0x0
0x0: Auto control disabled
0x1: DPLL4 is automatically put in low power stop mode
when none of the 96 MHz and 54 MHz clocks are
required anymore. It is also restarted automatically.
2:0 AUTO_CORE_DPLL DPLL3 automatic control; Other enums: Reserved RW 0x0
0x0: Auto control disabled
0x1: DPLL3 is automatically put in low power stop mode
when the CORE clock is not required anymore. It is also
restarted automatically.
0x5: DPLL3 is automatically put in idle bypass low power
mode when the CORE clock is not required anymore. It is
also restarted automatically.
Table 3-196. Register Call Summary for Register CM_AUTOIDLE_PLL
PRCM Functional Description
• DPLL Modes : [0] [1] [2] [3]
• DPLL Source-Clock Controls : [4] [5]
PRCM Basic Programming Model
• DPLL Clock Control Registers : [6]
PRCM Register Manual
• Clock_Control_Reg_CM Register Summary : [7]
503 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
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