Texas Instruments OMAP36 Series, Technical Reference Manual

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PRCM Register Manual
Table 3-184. CM_CLKSEL_WKUP
Address Offset 0x0000 0040
Physical Address 0x4800 4C40 Instance WKUP_CM
Description WAKEUP domain modules source clock selection.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED
CLKSEL_RM
CLKSEL_GPT1
Bits Field Name Description Type Reset
31:7 RESERVED Write 0s for future compatibility. Read returns 0. R 0x0000000
6:3 RESERVED Reserved for non-GP devices RW 0x2
2:1 CLKSEL_RM Selects the Reset Manager clock; Other enums: RW 0x1
Reserved
0x1: RM_ICLK is L4_CLK divided by 1
0x2: RM_ICLK is L4_CLK divided by 2
0 CLKSEL_GPT1 Selects GPTIMER 1 source clock RW 0x0
0x0: source is 32K_FCLK
0x1: source is SYS_CLK
Table 3-185. Register Call Summary for Register CM_CLKSEL_WKUP
PRCM Functional Description
• Interface and Peripheral Functional Clock Configurations : [0]
PRCM Basic Programming Model
• CM_CLKSEL_ <domain_name> (Clock Select Register) : [1]
PRCM Register Manual
• WKUP_CM Register Summary : [2]
3.8.1.8 Clock_Control_Reg_CM Registers
3.8.1.8.1 Clock_Control_Reg_CM Register Summary
Table 3-186. Clock_Control_Reg_CM Register Summary
Register Name Type Register Width Address Offset Physical Address Reset Type
(Bits)
CM_CLKEN_PLL RW 32 0x0000 0000 0x4800 4D00 W
CM_CLKEN2_PLL RW 32 0x0000 0004 0x4800 4D04 W
CM_IDLEST_CKGEN R 32 0x0000 0020 0x4800 4D20 C
CM_IDLEST2_CKGEN R 32 0x0000 0024 0x4800 4D24 C
CM_AUTOIDLE_PLL RW 32 0x0000 0030 0x4800 4D30 W
CM_AUTOIDLE2_PLL RW 32 0x0000 0034 0x4800 4D34 W
CM_CLKSEL1_PLL RW 32 0x0000 0040 0x4800 4D40 W
CM_CLKSEL2_PLL RW 32 0x0000 0044 0x4800 4D44 W
CM_CLKSEL3_PLL RW 32 0x0000 0048 0x4800 4D48 W
CM_CLKSEL4_PLL RW 32 0x0000 004C 0x4800 4D4C W
CM_CLKSEL5_PLL RW 32 0x0000 0050 0x4800 4D50 W
497 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
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