Texas Instruments OMAP36 Series, Technical Reference Manual

Page: 507 / 3738

Public Version
www.ti.com
PRCM Register Manual
Table 3-203. CM_CLKSEL3_PLL
Address Offset 0x0000 0048
Physical Address 0x4800 4D48 Instance Clock_Control_Reg_CM
Description This register controls the selection of the master clock frequencies.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED DIV_96M
Bits Field Name Description Type Reset
31:5 RESERVED Write 0s for future compatibility. Read returns 0. R 0x0000000
4:0 DIV_96M 96 MHz clock divider factor M2 (1 up to 31); Other RW 0x01
enums: Reserved
0x1: 96 MHz clock is DPLL4 clock divided by 1
0x2: 96 MHz clock is DPLL4 clock divided by 2
0x3: 96 MHz clock is DPLL4 clock divided by 3
0x4: 96 MHz clock is DPLL4 clock divided by 4
0x5: 96 MHz clock is DPLL4 clock divided by 5
0x6: 96 MHz clock is DPLL4 clock divided by 6
0x7: 96 MHz clock is DPLL4 clock divided by 7
0x8: 96 MHz clock is DPLL4 clock divided by 8
0x9: 96 MHz clock is DPLL4 clock divided by 9
0xA: 96 MHz clock is DPLL4 clock divided by 10
0xB: 96 MHz clock is DPLL4 clock divided by 11
0xC: 96 MHz clock is DPLL4 clock divided by 12
0xD: 96 MHz clock is DPLL4 clock divided by 13
0xE: 96 MHz clock is DPLL4 clock divided by 14
0xF: 96 MHz clock is DPLL4 clock divided by 15
0x10: 96 MHz clock is DPLL4 clock divided by 16
0x11: 96 MHz clock is DPLL4 clock divided by 17
0x12: 96 MHz clock is DPLL4 clock divided by 18
0x13: 96 MHz clock is DPLL4 clock divided by 19
0x14: 96 MHz clock is DPLL4 clock divided by 20
0x15: 96 MHz clock is DPLL4 clock divided by 21
0x16: 96 MHz clock is DPLL4 clock divided by 22
0x17: 96 MHz clock is DPLL4 clock divided by 23
0x18: 96 MHz clock is DPLL4 clock divided by 24
0x19: 96 MHz clock is DPLL4 clock divided by 25
0x1A: 96 MHz clock is DPLL4 clock divided by 26
0x1B: 96 MHz clock is DPLL4 clock divided by 27
0x1C: 96 MHz clock is DPLL4 clock divided by 28
0x1D: 96 MHz clock is DPLL4 clock divided by 29
0x1E: 96 MHz clock is DPLL4 clock divided by 30
0x1F: 96 MHz clock is DPLL4 clock divided by 31
Table 3-204. Register Call Summary for Register CM_CLKSEL3_PLL
PRCM Basic Programming Model
• CM_CLKSELn_PLL (DPLL Clock Selection Register) : [0]
PRCM Register Manual
• Clock_Control_Reg_CM Register Summary : [1]
507 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated