Texas Instruments OMAP36 Series, Technical Reference Manual

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PRCM Basic Programming Model
3.6.2.2.2 CM_CLKOUT_CTRL (Clock Out Control Register)
The CM clock out control register provides control over the device output clock sys_clkout2, which can be
used externally for functional or test purposes. The register allows the following:
• Selection of the source clock for sys_clkout2:
– CORE_CLK
– CM_SYS_CLK
– 96-MHz clock
– 54-MHz clock
• Dividing-down the selected source clock by 1, 2, 4, 8, or 16
• Enabling/disabling of the gating of sys_clkout2
3.6.2.3 DPLL Clock Control Registers
A set of registers controls the clock features of the five DPLLs (DPLL1, DPLL2, DPLL3, DPLL4, and
DPLL5):
• CM_CLKSELn_PLL_<processor_name>
• CM_CLKSELn_PLL
• CM_CLKEN_PLL_<processor_name>
• CM_CLKEN_PLL
• CM_AUTOIDLE_PLL_<processor_name>
• CM_AUTOIDLE_PLL
• CM_IDLEST_PLL_<processor_name>
• CM_IDLEST_CKGEN
• CM_IDLEST2_CKGEN
The following sections describe the purposes of these registers.
3.6.2.3.1 CM_CLKSELn_PLL_ <processor_name> (Processor DPLL Clock Selection Register)
The processor DPLL clock selection register controls the clock configuration of DPLL1 and DPLL2,
including the following features:
• The multiplier (M) and divider (N) values of the DPLL
• Selection of the fast bypass clock (CORE_CLK or CORE_CLK/2) in bypass mode
• Configuration of DPLL output clock divider values (M2 factor)
The device has four DPLL clock selection registers for DPLL1 and DPLL2:
• CM_CLKSEL1_PLL_MPU : DPLL1 multiplier, divider, and fast bypass clock selection
• CM_CLKSEL2_PLL_MPU : DPLL1 output clock divider selection
• CM_CLKSEL1_PLL_IVA2 : DPLL2 multiplier, divider, and fast bypass clock selection
• CM_CLKSEL2_PLL_IVA2 : DPLL2 output clock divider selection
3.6.2.3.2 CM_CLKSELn_PLL (DPLL Clock Selection Register)
The DPLL clock selection register controls the clock configuration for DPLL3, DPLL4, and DPLL5,
including the following features:
• The multiplier (M) and divider (N) values of the DPLL
• Configuration of DPLL output clock divider values
The device has the following DPLL clock selection registers for DPLL3, DPLL4, and DPLL5:
• CM_CLKSEL1_PLL : DPLL3 multiplier, divider, and output clock division configuration. Source selection
for the 54-MHz and 48-MHz clock (48M_FCLK) between DPLL4 output and sys_altclk.
• CM_CLKSEL2_PLL : DPLL4 multiplier and divider configuration
• CM_CLKSEL3_PLL : Divider configuration for 96-MHz clock (96M_FCLK)
• CM_CLKSEL4_PLL : DPLL5 multiplier and divider configuration
403 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
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