Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 471 / 3738

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PRCM Register Manual
Bits Field Name Description Type Reset
18:8 MPU_DPLL_MULT DPLL1 multiplier factor (0 to 2047) RW 0x000
7 RESERVED Write 0s for future compatibility. Read returns 0. R 0x0
6:0 MPU_DPLL_DIV DPLL1 divider factor (0 to 127) RW 0x00
Table 3-130. Register Call Summary for Register CM_CLKSEL1_PLL_MPU
PRCM Functional Description
• Processor Clock Configurations : [0] [1]
• Interface and Peripheral Functional Clock Configurations : [2] [3]
PRCM Basic Programming Model
• CM_CLKSELn_PLL_ <processor_name> (Processor DPLL Clock Selection Register) : [4]
• CM_CLKEN_PLL_<processor_name> (Processor DPLL Clock Enable Register) : [5]
PRCM Use Cases and Tips
• Switch VDD1 OPPs : [6] [7] [8] [9]
PRCM Register Manual
• MPU_CM Register Summary : [10]
• MPU_CM Registers :
Table 3-131. CM_CLKSEL2_PLL_MPU
Address Offset 0x0000 0044
Physical Address 0x4800 4944 Instance MPU_CM
Description This register provides controls over the MPU DPLL.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
MPU_DPLL_CLKOUT_DIV
471 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
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