Texas Instruments OMAP36 Series, Technical Reference Manual

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PRCM Functional Description
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Table 3-60. Interface Clock Configuration Controls
Module Clock Reference Multiplier Divider (Factor) Configuration Bits
Clock (Factor)
DPLL3 CLKOUT SYS_CLK M (0 ... 2047) PRCM. CM_CLKSEL1_PLL [26:16]
CORE_DPLL_MULT
CLKOUTX2 N (0 ... 127) PRCM. CM_CLKSEL1_PLL [14:8]
CORE_DPLL_ DIV
CORE_CLK CORE_CLK CLKOUT M2 (1 ... 31) PRCM. CM_CLKSEL1_PLL [31 :27]
CORE_DPLL_CLKOUT_DIV
COREX2_CLK CLKOUTX2
L3 L3_ICLK CORE_CLK DIV_L3 (1 ... 2) PRCM. CM_CLKSEL_CORE [1:0]
interconnect CLKSEL_L3
L4 L4_ICLK L3_ICLK DIV_L4 (1 ... 2) PRCM. CM_CLKSEL_CORE [3:2]
interconnect CLKSEL_L4
RM clock RM_L4_ICLK L4_ICLK DIV_RM (1 ... 2) PRCM. CM_CLKSEL_WKUP [2:1]
CLKSEL_RM
SGX_FCLK frequencies are configured depending on the source clock as:
• f
SGX_FCLK
= f
CORE_CLK
/DIV_SGX
• f
SGX_FCLK
= f
COREX2_CLK
/DIV2_SGX
• f
SGX_FCLK
= f
SGX_192M_FCLK
• f
SGX_FCLK
= f
CM_96M_FCLK
DPLL1_FCLK (bypass mode) and DPLL2_FCLK (bypass mode) frequencies are configured as:
• f
DPLL1_FCLK
= f
CORE_CLK
/DIV_DPLL1
• f
DPLL2_FCLK
= f
CORE_CLK
/DIV_DPLL2
Table 3-61 identifies the functional clocks, their reference clocks, and the control bits for configuration of
the functional clock frequencies.
Table 3-61. Functional Clock Configuration Controls
Module Clock Reference Divider (Factor) Configuration Bits
Clock
SGX SGX_FCLK CORE_CLK DIV_SGX (2, 3, 4, PRCM. CM_CLKSEL_SGX [2:0] CLKSEL_SGX
6)
COREX2_CLK DIV2_SGX (3, 5) PRCM. CM_CLKSEL_SGX [2:0] CLKSEL_SGX
SGX_192M_FC PRCM. CM_CLKSEL_SGX [2:0] CLKSEL_SGX
LK
CM_96M_FCLK PRCM. CM_CLKSEL_SGX [2:0] CLKSEL_SGX
MPU HS DPLL1_FCLK CORE_CLK DIV_DPLL1 (1, 2, PRCM. CM_CLKSEL1_PLL_MPU [20:19]
bypass 4) MPU_CLK_SRC
IVA2 HS DPLL2_FCLK CORE_CLK DIV_DPLL2 (1, 2, PRCM. CM_CLKSEL1_PLL_IVA2 [20:19]
bypass 4) IVA2_CLK_SRC
The rest of the functional clocks are issued from DPLL4 and DPLL5 and remain invariable, regardless of
the interface clock configuration. In all clock configurations, any divider ratio to generate functional clocks
is applicable, provided it complies with the maximum frequency specification.
CAUTION
Before any transition to OPP50, set the DPLL2 bypass clock to CORE_CLK/2
in the
CM_CLKSEL1_PLL_IVA2 [20:19] IVA2_CLK_SRC bit field. During the
relock phase, the DSP clock is 200 MHz. This has no effect on performance
because the DPLL2 relock time is only a few µs.
Always set the DPLL1 bypass clock to CORE_CLK/1 in the
CM_CLKSEL1_PLL_MPU [20:19] MPU_CLK_SRC bit field.
352 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
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