Texas Instruments OMAP36 Series, Technical Reference Manual

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PRCM Register Manual
Table 3-152. CM_AUTOIDLE3_CORE
Address Offset 0x0000 0038
Physical Address 0x4800 4A38 Instance CORE_CM
Description This register controls the automatic control of the CORE modules interface clock activity.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
RESERVED
AUTO_USBTLL
Bits Field Name Description Type Reset
31:3 RESERVED Write 0s for future compatibility. Read returns 0. R 0x00000000
2 AUTO_USBTLL USB TLL auto clock control. RW 0x0
0x0: USB TLL interface clock is unrelated to the domain
state transition.
0x1: USB TLL interface clock is automatically enabled or
disabled along with the domain state transition.
1:0 RESERVED Write 0s for future compatibility. Read returns 0. R 0x0
Table 3-153. Register Call Summary for Register CM_AUTOIDLE3_CORE
PRCM Basic Programming Model
• CM_AUTOIDLE_ <domain_name> (Autoidle Register) : [0]
PRCM Register Manual
• CORE_CM Register Summary : [1]
Table 3-154. CM_CLKSEL_CORE
Address Offset 0x0000 0040
Physical Address 0x4800 4A40 Instance CORE_CM
Description CORE modules clock selection.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED
RESERVED CLKSEL_L4 CLKSEL_L3
CLKSEL_96M
CLKSEL_GPT11 CLKSEL_GPT10
Bits Field Name Description Type Reset
31:14 RESERVED Write 0s for future compatibility. Read returns 0. R 0x00000
13:12 CLKSEL_96M Selects the 96 MHz clock; Other enums: Reserved. RW 0x1
0x1: The clock 96 MHz is the DPLL4_M2_CLK divided by
1
0x2: The clock 96 MHz is the DPLL4_M2_CLK divided by
2
11:8 RESERVED Write the reset value, read returns reset value. RW 0x1
485 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
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