Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 473 / 3738

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PRCM Register Manual
Bits Field Name Description Type Reset
31:2 RESERVED Write 0s for future compatibility. Read returns 0. R 0x00000000
1:0 CLKTRCTRL_MPU Controls the clock state transition of the MPU clock RW 0x0
domain.
0x0: Automatic transition is disabled
0x1: Reserved
0x2: Start a software supervised wake-up transition on
the domain
0x3: Automatic transition is enabled. Transition is
supervised by the HardWare.
Table 3-134. Register Call Summary for Register CM_CLKSTCTRL_MPU
PRCM Basic Programming Model
• CM_CLKSTCTRL_ <domain_name> (Clock State Control Register) : [0]
PRCM Register Manual
• MPU_CM Register Summary : [1]
Table 3-135. CM_CLKSTST_MPU
Address Offset 0x0000 004C
Physical Address 0x4800 494C Instance MPU_CM
Description This register provides a status on the clock activity in the domain (MPU DPLL output clock).
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
CLKACTIVITY_MPU
Bits Field Name Description Type Reset
31:1 RESERVED Write 0s for future compatibility. Read returns 0. R 0x00000000
0 CLKACTIVITY_MPU Clock activity status R 0x0
0x0: No domain clock activity
0x1: Domain clock is active
Table 3-136. Register Call Summary for Register CM_CLKSTST_MPU
PRCM Basic Programming Model
• CM_CLKSTST_ <domain_name> (Clock State Status Register) : [0]
PRCM Register Manual
• MPU_CM Register Summary : [1]
3.8.1.5 CORE_CM Registers
3.8.1.5.1 CORE_CM Register Summary
Table 3-137. CORE_CM Register Summary
Register Name Type Register Width Address Offset Physical Address Reset Type
(Bits)
CM_FCLKEN1_CORE RW 32 0x0000 0000 0x4800 4A00 W
473 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
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