Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 409 / 3738

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PRCM Basic Programming Model
3.6.2.4.6 CM_CLKSTCTRL_ <domain_name> (Clock State Control Register)
The clock state control register holds a CLKTRCTRL_<clock domain> bit field for each clock domain in the
power domain. It controls the hardware- and software-supervised state transitions between active and
inactive states.
Table 3-90 lists the clock state transition settings.
Table 3-90. Clock State Transition Settings
CM_CLKSTCTRL_<pwr domain>. Description
CLKTRCTRL_<clk domain>
0x0 The automatic hardware-supervised mode is disabled. The clocks in a clock domain
cannot be cut automatically. This prevents any power transition on the power domain.
0x1 Starts software-supervised (forced) sleep transition on the domain. All clocks in the
clock domain are automatically cut whenever the initiators in the modules are in
standby mode.
0x2 Starts software-supervised (forced) wake-up transition on the domain. The clocks in the
clock domain are restarted.
0x3 The automatic hardware-supervised mode is enabled, and the clocks in the clock
domain are automatically cut whenever the modules and subsystem in the clock
domain are in idle or standby mode and the domain dependencies are met.
The hardware-supervised mode and the software-supervised (forced) sleep mode are mutually exclusive.
It is a software decision to program one mode or another, and the software programs the PRCM module
accordingly.
The hardware-supervised mode is coupled to the sleep and wake-up dependencies programmed in the
PRCM module, whereas the software-supervised mode must be independent of those dependencies.
Therefore, the sleep and wake-up dependencies must be disabled before the software forces a sleep
transition on a power domain; otherwise, the forced-domain will be wakened immediately because of the
wake-up dependency.
The device has the following clock state control registers:
• CM_CLKSTCTRL_MPU : MPU subsystem clock domain
• CM_CLKSTCTRL_CORE : L3, L4, and D2D clock domains
• CM_CLKSTCTRL_CAM : Camera subsystem clock domain
• CM_CLKSTCTRL_DSS : DSS clock domain
• CM_CLKSTCTRL_PER : Peripherals clock domain
• CM_CLKSTCTRL_NEON : NEON clock domain
• CM_CLKSTCTRL_IVA2 : IVA2.2 clock domain
• CM_CLKSTCTRL_SGX : Graphics clock domain
• CM_CLKSTCTRL_EMU : Emulation clock domain
• CM_CLKSTCTRL_USBHOST : HS USB Host clock domain
The CORE domain has three clock domains (L3, L4, and D2D); it does not have forced sleep and forced
wake-up ability.
Although the sleep transition in the MPU power domain cannot be initiated by software using this register,
a software-initiated forced wake-up capability exists. This can be used to wake up the MPU power domain
if it does not wake up when the CORE power domain wakes up (the MPU wake-up-dependency
PM_WKDEP_MPU [0] EN_CORE bit is set to 0).
If the hardware-supervised mode is enabled, the following occur:
• The MPU domain clock is automatically cut if the MPU executes the wait-for-interrupt instruction.
• The IVA2 domain clock is automatically cut when the DSP completes its idle procedure, and the
IVA2.2 subsystem is ready for standby.
• The L3 domain clock is automatically cut when all initiators are in standby mode and slave ports are
idled.
• The L4 domain clock is automatically cut when all peripherals and slave ports are idled.
• The DSS interface clock is automatically cut when it stops fetching data from the frame buffer
(provided the MPU is also in standby mode, if sleep dependency in the MPU power domain is
409 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
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