Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 538 / 3738

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PRCM Register Manual
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Bits Field Name Description Type Reset
1:0 MUX_CTRL Selection of ATCLK.FCLK, PCLK.FCLK and PCLKx2.FCLK RW 0x0
source clock
0x0: ATCLK, PCLK and PCLKx2 source clock is SYS_CLK
0x1: ATCLK, PCLK and PCLKx2 source clock is
EMU_CORE_ALWON_CLK
0x2: ATCLK, PCLK and PCLKx2 source clock is
EMU_PER_ALWON clock
0x3: ATCLK, PCLK and PCLKx2 source clock is
EMU_MPU_ALWON_CLK
Table 3-264. Register Call Summary for Register CM_CLKSEL1_EMU
PRCM Register Manual
• EMU_CM Register Summary : [0]
Table 3-265. CM_CLKSTCTRL_EMU
Address Offset 0x0000 0048
Physical Address 0x4800 5148 Instance EMU_CM
Description This register allows to enable or disable SW and HW supervised transition between ACTIVE and
INACTIVE states.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
CLKTRCTRL_EMU
Bits Field Name Description Type Reset
31:2 RESERVED Write 0s for future compatibility. Read returns 0. R 0x00000000
1:0 CLKTRCTRL_EMU Controls the clock state transition of the EMULATION RW 0x2
clock domain.
0x0: Reserved
0x1: Start a software supervised sleep transition on the
domain
0x2: Start a software supervised wake-up transition on
the domain or maintain emulation domain active. (force
wakeup has to be kept asserted to keep Emulation
domain ON)
0x3: Automatic transition is enabled. Transition is
supervised by the HardWare.
Table 3-266. Register Call Summary for Register CM_CLKSTCTRL_EMU
PRCM Functional Description
• Device Wake-Up Events : [0] [1] [2]
PRCM Basic Programming Model
• CM_CLKSTCTRL_ <domain_name> (Clock State Control Register) : [3]
PRCM Register Manual
• EMU_CM Register Summary : [4]
538 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
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