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PRCM Register Manual
Table 3-111. CM_CLKSTCTRL_IVA2
Address Offset
0x0000 0048
Physical Address
0x4800 4048
Instance
IVA2_CM
Description
This register enables the domain power state transition. It controls the HW supervised domain power
state transition between ACTIVE and INACTIVE states.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
CLKTRCTRL_IVA2
Bits
Field Name
Description
Type
Reset
31:2
RESERVED
Write 0s for future compatibility. Read returns 0.
R
0x00000000
1:0
CLKTRCTRL_IVA2
Controls the clock state transition of the IVA2 clock
RW
0x0
domain.
0x0: Automatic transition is disabled
0x1: Start a software supervised sleep transition on the
domain
0x2: Start a software supervised wake-up transition on
the domain
0x3: Automatic transition is enabled. Transition is
supervised by the HardWare.
Table 3-112. Register Call Summary for Register CM_CLKSTCTRL_IVA2
PRCM Functional Description
•
:
PRCM Basic Programming Model
•
CM_CLKSTCTRL_ <domain_name> (Clock State Control Register)
PRCM Register Manual
•
Table 3-113. CM_CLKSTST_IVA2
Address Offset
0x0000 004C
Physical Address
0x4800 404C
Instance
IVA2_CM
Description
This register provides a status on the clock activity in the domain (IVA2 DPLL output clock).
Type
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
CLKACTIVITY_IVA2
465
SWPU177N – December 2009 – Revised November 2010
Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated
