Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 486 / 3738

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PRCM Register Manual
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Bits Field Name Description Type Reset
7 CLKSEL_GPT11 Selects GPTIMER 11 source clock RW 0x0
0x0: source is CM_32K_CLK
0x1: source is CM_SYS_CLK
6 CLKSEL_GPT10 Selects GPTIMER 10 source clock RW 0x0
0x0: source is CM_32K_CLK
0x1: source is CM_SYS_CLK
5:4 RESERVED Write 0s for future compatibility. Read returns 0. R 0x0
3:2 CLKSEL_L4 Selects Peripherals interconnect clock (L4_CLK); Other RW 0x1
enums: Reserved
0x1: L4_CLK is L3_CLK divided by 1 (boot mode only)
0x2: L4_CLK is L3_CLK divided by 2
1:0 CLKSEL_L3 Selects L3 interconnect clock (L3_CLK); Other enums: RW 0x1
Reserved
0x1: L3_CLK is CORE_CLK divided by 1
0x2: L3_CLK is CORE_CLK divided by 2
Table 3-155. Register Call Summary for Register CM_CLKSEL_CORE
PRCM Functional Description
• PRM Source-Clock Controls : [0] [1] [2] [3]
• Interface and Peripheral Functional Clock Configurations : [4] [5]
PRCM Basic Programming Model
• CM_CLKSEL_ <domain_name> (Clock Select Register) : [6]
• Enabling and Disabling the Interface Clocks : [7]
PRCM Register Manual
• CORE_CM Register Summary : [8]
Table 3-156. CM_CLKSTCTRL_CORE
Address Offset 0x0000 0048
Physical Address 0x4800 4A48 Instance CORE_CM
Description This register enables the domain power state transition. It controls the HW supervised domain power
state transition between ACTIVE and INACTIVE states.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
CLKTRCTRL_L4 CLKTRCTRL_L3
Bits Field Name Description Type Reset
31:4 RESERVED Write 0s for future compatibility. Read returns 0. R 0x0000000
3:2 CLKTRCTRL_L4 Controls the clock state transition of the L4 clock domain. RW 0x0
0x0: Automatic transition is disabled
0x1: Reserved
0x2: Reserved
0x3: Automatic transition is enabled. Transition is
supervised by the HardWare.
486 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
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