Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 427 / 3738

prcm-086
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Is the Interface
source clock
selectable
Start
Program the corresponding
CM_CLKSEL register to
select the source clock
Yes
No
Set the corresponding
CM_ICLKEN_<domain>
EN_<module> bit to 1
Yes
No
Set
module interface
clock to AUTOIDLE
mode
Set the corresponding
CM_AUTOIDLE_<domain>
AUTO_<module> bit to 1
Are the
Clock domain
Idle Conditions*
satisfied ?
Yes
No
End
Set the corresponding
CM_ICLKEN_<domain>
EN_<module> bit to 1
Start
Module interface clock
is running
No
Module interface
clock is gated
Are Clock domain
Idle Conditions*
satisfied?
Yes
Module
interface clock
can be gated
Test the module
interface clock
CLOCKACTIVITY bit
Yes
No
End
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Is
module in
idle state ?
Is module
interface clock
set to AUTOIDLE
mode
Yes
Yes
No
No
Set the corresponding
CM_ICLKEN_<domain>
EN_<module> bit to 0
No
Manually
idle the
clock
Yes
Set the corresponding
CM_ICLKEN_<domain>
EN_<module> bit to 0
Module IDLE mode
FORCED-IDLE
SMART-IDLE NO-IDLE
The software must ensure
coherence between
module IDLE state, clock
activity bit test and
clock gating request.
Hardware test
Hardware test
Hardware test
Module interface clock is gated
Module power domain is ON
Module interface
clock is running
* Clock domain Idle conditions are:
a. No other module sharing the same clock domain needs the clock.
(All modules of the clock domain are idled)
b. No wake-up event.
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PRCM Basic Programming Model
Figure 3-92. Interface Clock Basic Programming Model
The frequency ratio between the CORE_CLK, the L3_ICLK, and the L4_ICLK is configured by setting the
corresponding
CM_CLKSEL_CORE register bit fields. This configuration must be done before switching
DPLL3 to lock mode. In this way, the clock ratio is switched while DPLL3 is operating at system clock
frequency, and then only DPLL3 is switched to high-frequency locked mode.
If the configuration of the interface clock needs to be changed, first put DPLL3 in bypass mode, select the
new configuration, and then relock DPLL3.
NOTE: When performing frequency scaling, the clock division can be done directly by programming
the DPLL output divider. In this case, there is no need to change the configuration of the
interface clock.
3.6.6.1.3 Enabling and Disabling the Inactive State
The flow chart in Figure 3-93 shows how to put a domain into inactive state. This state is required before
any power transition from on state to retention or off state.
A domain is said to be in inactive state if:
• All the functional and interface clocks of the domain are gated (deactivated).
• All the initiator modules are in standby mode.
• All the dependent domains have reached their mute state. The sleep dependency between the power
domains is configured by programming the CM_SLEEPDEP_<domain> register.
The domain transition from active state to inactive state is effective only if the
CM_CLKSTCTRL_<domain> register is programmed for hardware-supervised state transition.
427 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated