Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 428 / 3738

prcm-087
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Start
All
functional and
interface clocks of the
domain are gated?
No
Yes
Program sleep dependencies of the
power domain in corresponding
CM_SLEEPDEP_<domain> register
Enable automatic sleep transition
control by setting corresponding
CM_CLKSTCTRL_<domain>.CLKTR
CTRL_<clock domain> bit field to 0x3
Power domain is in
ON power state
Disable interface and
functional clocks to all
modules of the power domain
End
Power domain is in retention
or OFF power state
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Start
Program wake-up dependencies of
the power domain in corresponding
PM_WKDEP_<domain> register
End
Power domain is in ON
power state
Attach module to processor wake-up
events group by setting corresponding
PM_<processor>GRPSEL_<domain>.
GRPSEL_<module> bit to 1
Enable wake-up event for the module
by setting PM_WKEN_<domain>.
EN_<module> bit to 0x1
Initiate power domain
sleep transition
Power domain is in retention
or OFF power state
Wake-up event
Enable interface clocks
to all modules of the
power domain
Enable Functional
clocks to all modules of
the power domain
Clear corresponding
PM_WKST_<domain>.
ST_<module> status bit to 0
AND junction
(All input conditions
must be satisfied)
Legend
Enable forced sleep transition
Control by setting corresponding
CM_CLKSTCTRL_<domain>.CLKTR
CTRL_<clock domain> bit field to 0x1
Power domain is in
ON power state
Program next power state of the
power domain by setting corresponding
PM_PWSTCTRL_<domain>.
POWERSTATE bit field
Public Version
PRCM Basic Programming Model
www.ti.com
The CM_CLKSTST_<domain> register identifies whether a power domain or a clock domain within the
power domain is accessible. A domain is inaccessible if its corresponding bit in the
CM_CLKSTST_<domain > register is set to 1.
Figure 3-93. Domain Inactive STATE Basic Programming Model
3.6.6.1.4 Processor Clock Control
The flow chart in Figure 3-94 shows the control sequence of the processor clock.
The processor source clock is generated by the dedicated processor DPLL (DPLL1 and DPLL2). After
power up, the processor DPLL is in bypass or stop mode. This means the processor clock is either the
system clock or is shut off.
The first step is to program the multiplier and divider ratios of the processor DPLL. Those two values are
written in the CM_CLKSEL1_PLL_<processor> register.
For frequency scaling, the processor DPLL integrates an additional divider to scale down the synthesized
clock. The value of this second divider is written in the CM_CLKSEL2_PLL_<processor> register. This
divider can be configured dynamically (while the processor executes instructions), and the DPLL output
clock is scaled without any glitches.
428 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated