Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 430 / 3738

prcm-088
P
ro
c
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rs
(M
P
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)
c
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c
k
p
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g
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m
m
in
g
Start
Yes No
Set AUTOIDLE mode?
Set corresponding
CM_AUTOIDLE_PLL_<processor>[2:0]
AUTO_<processor>_DPLL bit field to 0x1
Select divider ratio of DPLL1/DPLL2 high-speed
bypass clock (CORE_CLK) by setting corresponding
CM_CLKSEL1_PLL_<processor>[20:19]
<processor>_CLK_SRC bit
Set multiplier(M) and divider (N) factors for the
DPLL1/DPLL2s by setting the
CM_CLKSEL1_PLL_<processor>[18:8]
<processor>_DPLL_MULT and
CM_CLKSEL1_PLL_<processor>[6:0]
<processor>_DPLL_DIV bit fields
Set DPLL1/DPLL2 output clock divider factor by
setting the
CM_CLKSEL2_PLL_<processor>[4:0]
<processor>_DPLL_CLKOUT_DIV bit field
Set
DPLL to LOCK
mode?
No
Yes
Set corresponding
CM_CLKEN_PLL_<processor>[2:0]
EN_<processor>_DPLL bit field to 0x7
Set corresponding
CM_CLKEN_PLL_<processor>[2:0]
EN_<processor>_DPLL bit field to 0x5
Set
DPLL to BYPASS
mode?
No
Yes
DPLL
AUTOIDLE mode
is enabled?
Yes
No
Idle
conditions
satisfied?
Yes
No
No
End
DPLL in LOCK mode and
clock is running
DPLL in low-power STOP
mode and clock is
gated
DPLL is in low-power
BYPASS mode and
bypass clock is running
Hardware test
Hardware test
Public Version
PRCM Basic Programming Model
www.ti.com
Figure 3-94. Processor Clock Basic Programming Model
430 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated