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PRCM Basic Programming Model
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The device DPLL idle-status registers are:
•
: DPLL1 activity status
•
: DPLL2 activity status
3.6.2.4
Power-Domain Clock Control Registers
An identical set of registers controls the clock features of the power domains in the device:
•
CM_CLKSEL_<domain_name>
•
CM_FCLKEN_<domain_name>
•
CM_ICLKEN_<domain_name>
•
CM_AUTOIDLE_<domain_name>
•
CM_IDLEST_<domain_name>
•
CM_CLKSTCTRL_<domain_name>
•
CM_CLKSTST_<domain_name>
•
CM_SLEEPDEP_<domain_name>
The following sections describe the purposes of these registers.
3.6.2.4.1 CM_CLKSEL_ <domain_name> (Clock Select Register)
The clock select register controls the selection of the module or subsystem input clock frequency (except
for the processor modules). Therefore, it deals only with modules or subsystems for which the frequency
is scalable or selectable (the others have fixed and nonprogrammable frequencies). Both functional and
interface clocks can be scaled. In most cases, their value is a divided value from the DPLL3 (CORE) or
the DPLL4 (PER) output clock.
The device includes the following clock select registers:
•
: L3 and L4 interconnects, and GPTIMER10 and 11 functional clocks
•
: Camera subsystem functional clock
•
: DSS functional clock 1 and TV functional clock
•
: GPTIMER2, 3, 4, 5, 6, 7, 8, and 9 functional clocks
•
: SGX subsystem functional clock
•
: GPTIMER1 functional clock and reset manager counter clock
The 32-kHz functional clock (32K_FCLK) is selected when the device enters off mode. The functional
clock of the GPTIMER1 is selectable between the always-on 32K_FCLK and the system clock
(SYS_CLK), but it is used with the 32-kHz clock.
The
register controls the SGX functional clock source and divider ratio, which is
divided from the CORE_CLK source clock or COREX2_CLK.
summarizes SGX_FCLK
frequency for different configurations of the register field.
Table 3-88. GFX Functional Clock Ratio Settings
SGX_L3_FCLK
0x0
CORE_CLK/3
0x1
CORE_CLK/4
0x2
CORE_CLK/6
0x3
CM_96M_FCLK
0x4
SGX_192M_FCLK
0x5
CORE_CLK/2
0x6
COREX2_CLK/3
0x7
COREX2_CLK/5
406 Power, Reset, and Clock Management
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
