Texas Instruments OMAP36 Series, Technical Reference Manual

Page: 532 / 3738

Public Version
PRCM Register Manual
www.ti.com
Table 3-254. CM_CLKSEL_PER
Address Offset 0x0000 0040
Physical Address 0x4800 5040 Instance PER_CM
Description PER domain modules source clock selection.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
CLKSEL_GPT9 CLKSEL_GPT8 CLKSEL_GPT7 CLKSEL_GPT6 CLKSEL_GPT5 CLKSEL_GPT4 CLKSEL_GPT3 CLKSEL_GPT2
Bits Field Name Description Type Reset
31:8 RESERVED Write 0s for future compatibility. Read returns 0. R 0x000000
7 CLKSEL_GPT9 Selects GPTIMER 9 source clock RW 0x0
0x0: source is 32K_FCLK
0x1: source is SYS_CLK
6 CLKSEL_GPT8 Selects GPTIMER 8 source clock RW 0x0
0x0: source is 32K_FCLK
0x1: source is SYS_CLK
5 CLKSEL_GPT7 Selects GPTIMER 7 source clock RW 0x0
0x0: source is 32K_FCLK
0x1: source is SYS_CLK
4 CLKSEL_GPT6 Selects GPTIMER 6 source clock RW 0x0
0x0: source is 32K_FCLK
0x1: source is SYS_CLK
3 CLKSEL_GPT5 Selects GPTIMER 5 source clock RW 0x0
0x0: source is 32K_FCLK
0x1: source is SYS_CLK
2 CLKSEL_GPT4 Selects GPTIMER 4 source clock RW 0x0
0x0: source is 32K_FCLK
0x1: source is SYS_CLK
1 CLKSEL_GPT3 Selects GPTIMER 3 source clock RW 0x0
0x0: source is 32K_FCLK
0x1: source is SYS_CLK
0 CLKSEL_GPT2 Selects GPTIMER 2 source clock RW 0x0
0x0: source is 32K_FCLK
0x1: source is SYS_CLK
Table 3-255. Register Call Summary for Register CM_CLKSEL_PER
PRCM Basic Programming Model
• CM_CLKSEL_ <domain_name> (Clock Select Register) : [0]
PRCM Register Manual
• PER_CM Register Summary : [1]
532 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated