Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 524 / 3738

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PRCM Register Manual
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Table 3-245. PER_CM Register Summary
Register Name Type Register Width Address Offset Physical Address Reset Type
(Bits)
CM_FCLKEN_PER RW 32 0x0000 0000 0x4800 5000 W
CM_ICLKEN_PER RW 32 0x0000 0010 0x4800 5010 W
CM_IDLEST_PER R 32 0x0000 0020 0x4800 5020 C
CM_AUTOIDLE_PER RW 32 0x0000 0030 0x4800 5030 W
CM_CLKSEL_PER RW 32 0x0000 0040 0x4800 5040 W
CM_SLEEPDEP_PER RW 32 0x0000 0044 0x4800 5044 W
CM_CLKSTCTRL_PER RW 32 0x0000 0048 0x4800 5048 W
CM_CLKSTST_PER R 32 0x0000 004C 0x4800 504C C
3.8.1.11.2 PER_CM Registers
Table 3-246. CM_FCLKEN_PER
Address Offset 0x0000 0000
Physical Address 0x4800 5000 Instance PER_CM
Description Controls the modules functional clock activity.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
EN_GPT9 EN_GPT8 EN_GPT7 EN_GPT6 EN_GPT5 EN_GPT4 EN_GPT3 EN_GPT2
EN_WDT3
EN_GPIO6 EN_GPIO5 EN_GPIO4 EN_GPIO3 EN_GPIO2
EN_UART4 EN_UART3
EN_MCBSP4 EN_MCBSP3 EN_MCBSP2
Bits Field Name Description Type Reset
31:19 RESERVED Write 0s for future compatibility. Read returns 0. R 0x0000
18 EN_UART4 UART4 functional clock control. RW 0x0
0x0: UART 4 functional clock is disabled
0x1: UART 4 functional clock is enabled
17 EN_GPIO6 GPIO 6 functional clock control RW 0x0
0x0: GPIO 6 functional clock is disabled
0x1: GPIO 6 functional clock is enabled
16 EN_GPIO5 GPIO 5 functional clock control RW 0x0
0x0: GPIO 5 functional clock is disabled
0x1: GPIO 5 functional clock is enabled
15 EN_GPIO4 GPIO 4 functional clock control RW 0x0
0x0: GPIO 4 functional clock is disabled
0x1: GPIO 4 functional clock is enabled
14 EN_GPIO3 GPIO 3 functional clock control RW 0x0
0x0: GPIO 3 functional clock is disabled
0x1: GPIO 3 functional clock is enabled
13 EN_GPIO2 GPIO 2 functional clock control RW 0x0
0x0: GPIO 2 functional clock is disabled
0x1: GPIO 2 functional clock is enabled
12 EN_WDT3 WDTIMER 3 functional clock control. RW 0x0
0x0: WDTIMER 3 functional clock is disabled
0x1: WDTIMER 3 functional clock is enabled
524 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
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