Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 526 / 3738

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Table 3-248. CM_ICLKEN_PER
Address Offset 0x0000 0010
Physical Address 0x4800 5010 Instance PER_CM
Description Controls the modules interface clock activity.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
EN_GPT9 EN_GPT8 EN_GPT7 EN_GPT6 EN_GPT5 EN_GPT4 EN_GPT3 EN_GPT2
EN_WDT3
EN_GPIO6 EN_GPIO5 EN_GPIO4 EN_GPIO3 EN_GPIO2
EN_UART4 EN_UART3
EN_MCBSP4 EN_MCBSP3 EN_MCBSP2
Bits Field Name Description Type Reset
31:19 RESERVED Write 0s for future compatibility. Read returns 0. R 0x0000
18 EN_UART4 UART4 interface clock control. RW 0x0
0x0: UART 4 interface clock is disabled
0x1: UART 4 interface clock is enabled
17 EN_GPIO6 GPIO 6 interface clock control RW 0x0
0x0: GPIO 6 interface clock is disabled
0x1: GPIO 6 interface clock is enabled
16 EN_GPIO5 GPIO 5 interface clock control RW 0x0
0x0: GPIO 5 interface clock is disabled
0x1: GPIO 5 interface clock is enabled
15 EN_GPIO4 GPIO 4 interfface clock control RW 0x0
0x0: GPIO 4 interface clock is disabled
0x1: GPIO 4 interface clock is enabled
14 EN_GPIO3 GPIO 3 interface clock control RW 0x0
0x0: GPIO 3 interface clock is disabled
0x1: GPIO 3 interface clock is enabled
13 EN_GPIO2 GPIO 2 interface clock control RW 0x0
0x0: GPIO 2 interface clock is disabled
0x1: GPIO 2 interface clock is enabled
12 EN_WDT3 WDTIMER 3 interface clock control. RW 0x0
0x0: WDTIMER 3 interface clock is disabled
0x1: WDTIMER 3 interface clock is enabled
11 EN_UART3 UART3 interface clock control. RW 0x0
0x0: UART 3 interface clock is disabled
0x1: UART 3 interface clock is enabled
10 EN_GPT9 GPTIMER 9 interface clock control. RW 0x0
0x0: GPTIMER 9 interface clock is disabled
0x1: GPTIMER 9 interface clock is enabled
9 EN_GPT8 GPTIMER 8 interface clock control. RW 0x0
0x0: GPTIMER 8 interface clock is disabled
0x1: GPTIMER 8 interface clock is enabled
8 EN_GPT7 GPTIMER 7 interface clock control. RW 0x0
0x0: GPTIMER 7 interface clock is disabled
0x1: GPTIMER 7 interface clock is enabled
526 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
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