Texas Instruments OMAP36 Series, Technical Reference Manual

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PRCM Register Manual
Bits Field Name Description Type Reset
7 EN_GPT6 GPTIMER 6 interface clock control. RW 0x0
0x0: GPTIMER 6 interface clock is disabled
0x1: GPTIMER 6 interface clock is enabled
6 EN_GPT5 GPTIMER 5 interface clock control. RW 0x0
0x0: GPTIMER 5 interface clock is disabled
0x1: GPTIMER 5 interface clock is enabled
5 EN_GPT4 GPTIMER 4 interface clock control. RW 0x0
0x0: GPTIMER 4 interface clock is disabled
0x1: GPTIMER 4 interface clock is enabled
4 EN_GPT3 GPTIMER 3 interface clock control. RW 0x0
0x0: GPTIMER 3 interface clock is disabled
0x1: GPTIMER 3 interface clock is enabled
3 EN_GPT2 GPTIMER 2 interface clock control. RW 0x0
0x0: GPTIMER 2 interface clock is disabled
0x1: GPTIMER 2 interface clock is enabled
2 EN_MCBSP4 McBSP 4 interface clock control. RW 0x0
0x0: McBSP 4 interface clock is disabled
0x1: McBSP 4 interface clock is enabled
1 EN_MCBSP3 McBSP 3 interface clock control. RW 0x0
0x0: McBSP 3 interface clock is disabled
0x1: McBSP 3 interface clock is enabled
0 EN_MCBSP2 McBSP 2 interface clock control. RW 0x0
0x0: McBSP 2 interface clock is disabled
0x1: McBSP 2 interface clock is enabled
Table 3-249. Register Call Summary for Register CM_ICLKEN_PER
PRCM Functional Description
• PER Power Domain Clock Controls : [0]
PRCM Basic Programming Model
• CM_ICLKEN_ <domain_name> (Interface Clock Enable Register) : [1]
PRCM Register Manual
• PER_CM Register Summary : [2]
Table 3-250. CM_IDLEST_PER
Address Offset 0x0000 0020
Physical Address 0x4800 5020 Instance PER_CM
Description Modules access availability monitoring. This register is read only and automatically updated.
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
ST_GPT9 ST_GPT8 ST_GPT7 ST_GPT6 ST_GPT5 ST_GPT4 ST_GPT3 ST_GPT2
ST_WDT3
ST_GPIO6 ST_GPIO5 ST_GPIO4 ST_GPIO3 ST_GPIO2
ST_UART4 ST_UART3
ST_MCBSP4 ST_MCBSP3 ST_MCBSP2
527 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
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