Texas Instruments OMAP36 Series, Technical Reference Manual

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Source selection/division
sys_xtalout
sys_xtalin
PRCM.PRM_CLKSRC_CTRL[7:6]
SYSCLKDIV
CM_SYS_CLK
Hardware control Software control
PRCM.PRM_CLKSRC_CTRL[4:3]
AUTOEXTCLKMODE
sys_32k
CM_32K_CLK
SYS_CLK
32K_FCLK
OSC_SYS_CLK
HC
CL
CL
sys_boot6
PRCM.PRM_POLCTRL[1]
CLKREQ_POL
PRCM.PRM_CLKOUT_CTRL[7]
CLKOUT_EN
PRCM.PRM_POLCTRL[2]
CLKOUT_POL
sys_clkout1
sys_clkreq
HC
GS
GS
PRCM.PRM_CLKSETUP[15:0]
SETUP_TIME
HC
PRM_192M_ALWON_CLK
CM_96M_FCLK
96M_ALWON_FCLK
CL GS
prcm-056
CL GS
SGX_192M_FCLK
CL GS
PRCM.CM_CLKSEL_CORE[13:12]
CLKSEL_96M
Public Version
www.ti.com
PRCM Functional Description
Figure 3-60. Common PRM Source-Clock Controls
Table 3-45 shows the common source-clock gating controls for the PRM.
Table 3-45. Common PRM Source-Clock Gating Controls
Clock Name Reset Clock-Gating Control Gating Description
OSC_SYS_CLK Running PRCM. PRM_CLKSRC_CTRL [4:3] Gated when the oscillator is programmed
AUTOEXTCLKMODE and device power state and to power down with the device
sys_clkreq sleep/retention/off transition
sys_clkout1 Running PRCM. PRM_CLKOUT_CTRL [7] CLKOUT_EN and Active when OSC_SYS_CLK is active,
PRCM. PRM_POLCTRL [2] CLKOUT_POL and sys_clkout1 is enabled, and sys_clkreq is
sys_clkreq asserted
SYS_CLK Running Activated after clksetup_count_overflow Active when OSC_SYS_CLK is active and
the SYS_CLK setup time is up
CM_SYS_CLK Running PRCM. CM_CLKSEL_CORE [6] CLKSEL_GPT10, Active if it is the source clock of the
PRCM. CM_CLKSEL_CORE [7] CLKSEL_GPT11, GPT10_FCLK or GPT11_FCLK and the
and depends on the clock-gating conditions of functional clock is active
GPT10_FCLK and GPT11_FCLK
32K_FCLK Running None Always-active clock from the sys_32k input
pin
CM_32K_CLK Running PRCM. CM_CLKSEL_CORE [6] CLKSEL_GPT10, Active if it is the source clock of the
PRCM. CM_CLKSEL_CORE [7] CLKSEL_GPT11, GPT10_FCLK or GPT11_FCLK and the
and depends on the clock-gating conditions of functional clock is active
GPT10_FCLK and GPT11_FCLK
CM_96M_FCLK Gated CM_CLKSEL1_PLL [3] SOURCE_48M bit cleared, Active if the derived clocks (96M_FCLK,
and depends on the clock-gating condition of 48M_FCLK, and 12M_FCLK) are active or
96M_FCLK, 48M_FCLK, and 12M_FCLK when SGX has its functional clock enable
and its source is the 96MHz clock
335 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated