Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 637 / 3738

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PRCM Register Manual
Table 3-463. PRM_SRAM_PCHARGE
Address Offset 0x0000 0064
Physical Address 0x4830 7264 Instance Global_Reg_PRM
Description This register allows setting the pre-charge time of the SRAM.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED PCHARGE_TIME
Bits Field Name Description Type Reset
31:8 RESERVED Write 0s for future compatibility. Read returns 0. R 0x000000
7:0 PCHARGE_TIME Number of system clock cycles for the SRAM pre-charge RW 0x50
duration.
Table 3-464. Register Call Summary for Register PRM_SRAM_PCHARGE
PRCM Register Manual
• Global_Reg_PRM Register Summary : [0]
Table 3-465. PRM_CLKSRC_CTRL
Address Offset 0x0000 0070
Physical Address 0x4830 7270 Instance Global_Reg_PRM
Description This register provides control over the device source clock.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
RESERVED RESERVED
SYSCLKDIV
SYSCLKSEL
DPLL4_CLKINP_DIV
AUTOEXTCLKMODE
Bits Field Name Description Type Reset
31:9 RESERVED Write 0s for future compatibility. Read returns 0. R 0x000000
8 DPLL4_CLKINP_DIV This field controls the divider of the DPLL4 reference RW 0x0
clock.
0x0: The DPLL4 reference clock is the system clock
divided by 1.
0x1: The DPLL4 reference clock is the system clock
divided by 6.5.
7:6 SYSCLKDIV This field controls the system clock input divider RW 0x1
0x0: Reserved
0x1: Syst_clk is external clock / 1
0x2: Syst_clk is external clock / 2
0x3: Reserved
5 RESERVED Write 0s for future compatibility. Read returns 0. R 0x0
637 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
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