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PRCM Register Manual
Table 3-438. Global_Reg_PRM Register Summary (continued)
Register Name
Type
Register Width
Address Offset
Physical Address
Reset Type
(Bits)
RW
32
0x0000 0058
0x4830 7258
C
RW
32
0x0000 0060
0x4830 7260
W
RW
32
0x0000 0064
0x4830 7264
C
RW
32
0x0000 0070
0x4830 7270
C
R
32
0x0000 0080
0x4830 7280
C
RW
32
0x0000 0090
0x4830 7290
C
RW
32
0x0000 0094
0x4830 7294
C
RW
32
0x0000 0098
0x4830 7298
C
RW
32
0x0000 009C
0x4830 729C
C
RW
32
0x0000 00A0
0x4830 72A0
C
RW
32
0x0000 00B0
0x4830 72B0
W
RW
32
0x0000 00B4
0x4830 72B4
W
RW
32
0x0000 00B8
0x4830 72B8
W
RW
32
0x0000 00BC
0x4830 72BC
W
R
32
0x0000 00C0
0x4830 72C0
W
R
32
0x0000 00C4
0x4830 72C4
W
RW
32
0x0000 00D0
0x4830 72D0
W
RW
32
0x0000 00D4
0x4830 72D4
W
RW
32
0x0000 00D8
0x4830 72D8
W
RW
32
0x0000 00DC
0x4830 72DC
W
R
32
0x0000 00E0
0x4830 72E0
W
R
32
0x0000 00E4
0x4830 72E4
W
RW
32
0x0000 00F0
0x4830 72F0
W
RW
32
0x0000 00F4
0x4830 72F4
W
3.8.2.13.2 Global_Reg_PRM Registers
Table 3-439. PRM_VC_SMPS_SA
Address Offset
0x0000 0020
Physical Address
0x4830 7220
Instance
Global_Reg_PRM
Description
This register allows the setting of the I
2
C slave address of the Power IC device.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
SA1
RESERVED
SA0
Bits
Field Name
Description
Type
Reset
31:23
RESERVED
Write 0s for future compatibility. Read is undefined.
R
0x000
22:16
SA1
Set the I
2
C slave address value for the second (if any)
RW
0x00
Power IC device.
15:7
RESERVED
Write 0s for future compatibility. Read is undefined.
R
0x000
6:0
SA0
Set the I
2
C slave address value for the first Power IC
RW
0x00
device.
627
SWPU177N – December 2009 – Revised November 2010
Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated