Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 639 / 3738

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PRCM Register Manual
Table 3-468. Register Call Summary for Register PRM_OBS
PRCM Register Manual
• Global_Reg_PRM Register Summary : [0]
Table 3-469. PRM_VOLTSETUP1
Address Offset 0x0000 0090
Physical Address 0x4830 7290 Instance Global_Reg_PRM
Description This register allows setting the setup time of the VDD1 and VDD2 regulators. This register is used when
exiting OFF/RET/SLEEP mode (or enters OFF/RET/SLEEP mode) and when device manages the
sequencing of the voltages regulation steps.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETUP_TIME2 SETUP_TIME1
Bits Field Name Description Type Reset
31:16 SETUPTIME2 The value, in number of cycles of SYS_CLK, determines RW 0x0000
the setup duration of VDD2 regulator. The setup duration
is computed as = 8 x number of cycles of SYS_CLK set
in the register bit field.
15:0 SETUPTIME1 The value, in number of cycles of SYS_CLK, determines RW 0x0000
the setup duration of VDD1 regulator. The setup duration
is computed as = 8 x number of cycles of SYS_CLK set
in the register bit field.
Table 3-470. Register Call Summary for Register PRM_VOLTSETUP1
PRCM Functional Description
• Direct Control With VMODE Signals : [0]
• Device Off-Mode Sequences : [1] [2]
• Sleep Sequences : [3] [4]
• Wake-Up Sequences : [5] [6]
PRCM Basic Programming Model
• PRM_VOLTSETUP (Voltage Setup Time Register) : [7] [8] [9] [10] [11]
PRCM Use Cases and Tips
• Initialization Procedure : [12] [13]
PRCM Register Manual
• Global_Reg_PRM Register Summary : [14]
Table 3-471. PRM_VOLTOFFSET
Address Offset 0x0000 0094
Physical Address 0x4830 7294 Instance Global_Reg_PRM
Description This register allows controlling the sys_offmode signal upon wake-up from OFF mode when the OFF
sequence is supervised by the Power IC. This register allows setting the offset-time to de-assert
sys_offmode when exiting the OFF mode.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED OFFSET_TIME
Bits Field Name Description Type Reset
31:16 RESERVED Write 0s for future compatibility. Read returns 0. R 0x0000
15:0 OFFSET_TIME Number of 32kHz clock cycles for the OFF mode offset RW 0x0000
time
639 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
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