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PRCM Functional Description
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Device off-mode transition using only the SYS_OFF_MODE signal
3.5.7.4.1.1 Device Off-Mode Transition Without Using the SYS_OFF_MODE Signal
Each time the device enters I/O-pad-off configuration mode, the following sequence must be performed:
1. Software sets the PRCM.
[16]
EN_IO_CHAIN bit to enable the I/O wake-up scheme.
2. The MPU initiates the sleep sequence. When all sleep conditions are met, all domain clocks are shut
down. At this stage, all output pads are inactive and static.
3. The PRM configures the I/O daisy-chain for the wake-up detection scheme.
4. The CORE domain output is isolated.
When conditions for entering off mode are met, the PRM proceeds with the sequence.
5. It switches off all domains, including the CORE power domain, and then switches from active mode
pad configuration to off mode pad configuration.
6. It isolates the pads before the removal of VDD1 and VDD2.
7. It shuts down all analog cells (DPLL, DLL).
8. It switches to off all the DPLL power domains and the SR power domain.
9. It sends the off command for VDD1 to the voltage controller
10. It shuts down the SRAM LDOs.
11. The daisy chain is now ready to detect I/O pad wake-up events.
12. The PRM sends the off command for VDD1 to the voltage controller. Through I2C4, the voltage
controller requests the power IC to set VDD1 to the voltage corresponding to the
[7:0] OFF bit field. (A legacy mode exists where vmode pins can be used
instead of I2C4, depending on the
[4] SEL_VMODE bit. In this case, the PRM
asserts sys_nvmode1 and the power IC updates VDD1 to its previously programmed value.)
13. Upon reception of the I2C4 transaction acknowledge, and after waiting for the VDD1 regulator setup
time counter to expire (the
[15:0] SETUPTIME1 bit field), the PRM sends the off
command for VDD2 to the voltage controller. Through I2C4, the voltage controller requests the power
IC to set VDD2 to the voltage corresponding to
[7:0] OFF bit field. (If vmode
legacy mode is used, the PRM asserts sys_nvmode2 and the power IC restores VDD2 to its previously
programmed value.)
14. Upon reception of the I2C4 transaction acknowledge, and after waiting for the VDD2 regulator setup
time counter to expire (the
[31:16] SETUPTIME2 bit field), the PRM gates the
internal system clock.
15. It releases sys_clkreq and disables the system clock oscillator (if used).
16. The PRM ramps down the wake-up LDO to 1 V.
17. It waits for a wake-up event from the daisy chain or from an internal event (timer) from the WKUP
domain.
NOTE:
If an I/O pad toggles, when the I/O daisy-chain is already configured for the wake-up
detection scheme, and before off mode transition occurs, then a not real wake-up event is
logged in its padconf register.
NOTE:
The condition to release the PAD_OFF_MODE signal upon wakeup from off mode is
selected through the
[8] PAD_OFF_MODE_OVR bit. This signal can be
released by software after the software is restored by an interface such as GPIO.
3.5.7.4.1.2 Device Off-Mode Transition Using Only the SYS_OFF_MODE Signal
Depending on the external power IC capability and the user setting, VDD1 and VDD2 voltage control may
use the direct sys_off_mode signal and not send the commands through the I
2
C interface.
395
SWPU177N – December 2009 – Revised November 2010
Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated