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PRCM Basic Programming Model
3.6.4.3
PM_PREPWSTST_ <domain_name> (Previous Power State Status Register)
The previous power state status register indicates the power state entered during the last sleep transition.
The information in this register is useful when the domain switches back to on state (following a wake-up
transition). This register must only be read when the domain power state is on.
This register has the following bit fields:
•
LASTPOWERSTATEENTERED: Last domain power state entered after the last sleep transition
•
LASTLOGICSTATEENTERED: Last logic power state entered after the last sleep transition
•
LASTMEMORYSTATEENTERED: Last memory power state entered after the last sleep transition or
before the last memory change update
The device has the following previous power state status registers:
•
: The MPU power domain previous power state status
•
: The CORE power domain previous power state status
•
: The SGX power domain previous power state status
•
: The DSS power domain previous power state status
•
: The CAM power domain previous power state status
•
: The PER power domain previous power state status
•
: The NEON power domain previous power state status
•
: The IVA2 power domain previous power state status
•
PM_ PREPWSTST_USBHOST: The USBHOST power domain previous power state status
The previous power state status register for the MPU power domain indicates the previous domain, logic,
L1 cache (on or off), and L2 cache (on, retention, or off) power state.
The previous power state status register for the CORE power domain indicates the previous domain, logic
(on or off), and memory banks 1 and 2 (on, retention, or off) power state.
The previous power state status registers for the SGX, DSS, CAM, PER, NEON, USBHOST and EMU
power domains indicate the previous domain (on, inactive, retention, or off) power state. The SGX power
domain does not require a memory power state status, because the SGX memory state is not
programmable and reflects the power state.
The previous power state status register for the IVA2 power domain indicates the previous domain (on,
inactive, retention, or off), logic (on or off), L1 cache and flat memory (on, retention, or off), and L2 cache
and flat memory (on, retention, or off) power state status.
The current memory state depends on the setting of the PM_PWSTCTRL_<domain_name>
MEMONSTATE bit during the last wake-up transition or during the last memory change operation.
This register must be cleared by software by writing any value to it; this operation must be done when the
domain power state is on. Clearing this register does the following:
•
Resets the PM_PREPWSTST_<domain_name> LASTPOWERSTATEENTERED bit field and the
PM_PREPWSTST_<domain_name> LASTLOGICSTATEENTERED bit to the on state
•
Sets the bit fields corresponding to the last memory state of the power domain to the current memory
state
NOTE:
Performing a memory change (the PM_PWSTCTRL_<domain_name>[3]
MEMORYCHANGE bit for MPU, IVA2, and CORE) has the same effect as clearing this
register.
3.6.5 Voltage Management Registers
3.6.5.1
External Voltage Control Register Descriptions
3.6.5.1.1 PRM_VOLTSETUP (Voltage Setup Time Register)
The device has two voltage setup registers:
419
SWPU177N – December 2009 – Revised November 2010
Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated
