Texas Instruments OMAP36 Series, Technical Reference Manual

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PRCM Register Manual
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Table 3-431. PM_PREPWSTST_PER
Address Offset 0x0000 00E8
Physical Address 0x4830 70E8 Instance PER_PRM
Description This register provides a status on the PER domain previous power state. It indicates the state entered
during the last sleep transition.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
LASTLOGICSTATEENTERED
LASTPOWERSTATEENTERED
Bits Field Name Description Type Reset
31:3 RESERVED Write 0s for future compatibility. Read returns 0. R 0x00000000
2 LASTLOGICSTATEENTERED Last logic state entered RW 0x0
0x0: PER domain logic was previously OFF
0x1: PER domain logic was previously ON
1:0 LASTPOWERSTATEENTERED Last power state entered RW 0x0
0x0: PER domain was previously OFF
0x1: PER domain was previously in RETENTION
0x2: PER domain was previously INACTIVE
0x3: PER domain was previously ON
Table 3-432. Register Call Summary for Register PM_PREPWSTST_PER
PRCM Basic Programming Model
• PM_PREPWSTST_ <domain_name> (Previous Power State Status Register) : [0]
PRCM Register Manual
• PER_PRM Register Summary : [1]
3.8.2.12 EMU_PRM Registers
3.8.2.12.1 EMU_PRM Register Summary
Table 3-433. EMU_PRM Register Summary
Register Name Type Register Width Address Offset Physical Address Reset Type
(Bits)
RM_RSTST_EMU RW 32 0x0000 0058 0x4830 7158 C
PM_PWSTST_EMU RW 32 0x0000 00E4 0x4830 71E4 C
3.8.2.12.2 EMU_PRM Registers
624 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
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