Texas Instruments OMAP36 Series, Technical Reference Manual

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PRCM Register Manual
Table 3-434. RM_RSTST_EMU
Address Offset 0x0000 0058
Physical Address 0x4830 7158 Instance EMU_PRM
Description This register logs the different reset sources of the EMU domain. Each bit is set upon release of the
domain reset signal. Must be cleared by software.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
GLOBALCOLD_RST
DOMAINWKUP_RST
GLOBALWARM_RST
Bits Field Name Description Type Reset
31:3 RESERVED Write 0s for future compatibility. Read returns 0. R 0x00000000
2 DOMAINWKUP_RST Power domain wake-up reset RW 0x0
Read 0x0: No power domain wake-up reset.
Write 0x0: Status bit unchanged
Read 0x1: EMULATION domain has been reset following
an EMULATION power domain wake-up.
Write 0x1: Status bit is cleared to 0.
1 GLOBALWARM_RST Global warm reset RW 0x0
Read 0x0: No global warm reset.
Write 0x0: Status bit unchanged
Read 0x1: MPU domain has been reset upon a global
warm reset
Write 0x1: Status bit is cleared to 0.
0 GLOBALCOLD_RST Global cold reset RW 0x1
Read 0x0: No global cold reset.
Write 0x0: Status bit unchanged
Read 0x1: MPU domain has been reset upon a global
cold reset
Write 0x1: Status bit is cleared to 0.
Table 3-435. Register Call Summary for Register RM_RSTST_EMU
PRCM Basic Programming Model
• RM_RSTST_ <domain_name> (Reset Status Register) : [0]
PRCM Register Manual
• EMU_PRM Register Summary : [1]
625 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
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