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PRCM Basic Programming Model
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RSTTIME1: Minimum duration (by default, two cycles of the 32-kHz clock) of the global warm reset
(sys_nreswarm) assertion for external devices, such as flash memories. At power-up reset, DPLLs are
reset and the power domains are switched on and stabilized during this duration.
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RSTTIME2: Minimum duration (by default, 16 cycles of the RM_ICLK clock) to control power domain
resets when the domain clocks are on.
For global cold and warm resets, the reset is applied for the RS RSTTIME2 duration. In the
other cases, when a power domain individually goes from off to active, the reset is applied only for the
RSTTIME2 duration (plus the power domain wake-up duration).
RSTTIME1 and RSTTIME2 can be reprogrammed for different behavior after the initial power up.
3.6.3.1.2 RM_RSTCTRL_ <domain_name> (Reset Control Register)
The reset control register provides control over the local domain software reset.
Most device modules include an individual software reset that can be controlled using the related module
SYS_CONFIG register.
The RM_RSTCTRL_<domain_name> register is used for specific subsystems or modules that do not
support this local reset or that require a specific system control (the IVA2.2 subsystem).
The
register also handles the global software warm reset control.
The device includes the following reset control registers:
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: This register allows control of the assertion of the global software reset and the
DPLL3 software reset. These bits are automatically cleared. Assertion of the DPLL3 software reset
triggers a device global cold reset. The reset condition of this register depends on the bit field:
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The RST_GS bit is set on any global source of reset (warm or cold).
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The RST_DPLL3 bit is set only on a global cold source of reset.
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: IVA2 power domain software resets the IVA2.2 and SEQ subsystems. Both
subsystems are held under reset after power up and are released by software. The SEQ software
reset bit is reset to 1 (SEQ reset active) on an IVA2 domain power transition from off or retention to on.
3.6.3.1.3 RM_RSTST_ <domain_name> (Reset Status Register)
The reset status register logs any source that has generated a reset in the related power domain.
Depending on the domain, several causes of reset can be logged:
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Global device cold reset
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Global device warm reset
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Power domain transition (off to active, and inactive to active)
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Software reset
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Processor emulation reset
The
register logs the source of the global reset:
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VDD1/VDD2 voltage manager reset
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External warm reset
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MPU watchdog reset
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Global software reset and DPLL3 software reset
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Global cold reset
The device includes the following reset status registers:
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414
Power, Reset, and Clock Management
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
